X20C04
4K
X20C04
Nonvolatile Static RAM
512 x 8 Bit
FEATURES
DESCRIPTION
The Xicor X20C04 is a 512 x 8 NOVRAM featuring a
static RAM overlaid bit-for-bit with a nonvolatile electri-
cally erasable PROM (E
2
PROM). The X20C04 is fabri-
cated with advanced CMOS floating gate technology to
achieve low power and wide power-supply margin. The
X20C04 features the JEDEC approved pinout for byte-
wide memories, compatible with industry standard RAMs,
ROMs, EPROMs, and E
2
PROMs.
The NOVRAM design allows data to be easily trans-
ferred from RAM to E
2
PROM (store) and E
2
PROM to
RAM (recall). The store operation is completed in 5ms or
less and the recall operation is completed in 5µs or less.
Xicor NOVRAMS are designed for unlimited write
operations to RAM, either from the host or recalls from
E
2
PROM, and a minimum 1,000,000 store operations to
the E
2
PROM. Data retention is specified to be greater
than 100 years.
•
•
•
•
•
•
High Reliability
—Endurance: 1,000,000 Nonvolatile Store
Operations
—Retention: 100 Years Minimum
Power-on Recall
—E
2
PROM Data Automatically Recalled Into
SRAM Upon Power-up
Lock Out Inadvertent Store Operations
Low Power CMOS
—Standby: 250
µ
A
Infinite E
2
PROM Array Recall, and RAM Read
and Write Cycles
Compatible with X2004
PIN CONFIGURATION
PLASTIC
CERDIP
NC
LCC
PLCC
VCC
WE
NE
NC
NC
A7
NE
NC
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
X20C04 21
20
19
18
17
16
15
VCC
WE
NC
A8
NC
NC
OE
NC
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
5
6
7
8
9
4
3
2
1 32 31 30
29
28
27
26
A8
NC
NC
NC
OE
NC
CE
I/O7
I/O6
X20C04
(TOP VIEW)
25
24
23
22
10
11
12
13
21
14 15 16 17 18 19 20
I/O1
I/O2
VSS
NC
I/O3
I/O4
I/O5
3825 FHD F02
3825 FHD F03
©Xicor, Inc. 1992, 1995, 1996 Patents Pending
3825-2.8 7/31/97 T4/C0/D0 SH
1
Characteristics subject to change without notice
X20C04
PIN DESCRIPTIONS
Addresses (A
0
–A
8
)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When
CE
is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read and recall operations. Output
Enable LOW disables a store operation regardless of
the state of
CE, WE,
or
NE.
Data In/Data Out (I/O
0
–I/O
7
)
Data is written to or read from the X20C04 through the
I/O pins. The I/O pins are placed in the high impedance
state when either
CE
or
OE
is HIGH or when
NE
is LOW.
Write Enable (WE)
The Write Enable input controls the writing of data to
both the static RAM and stores to the E
2
PROM.
Nonvolatile Enable (NE)
The Nonvolatile Enable input controls all accesses to
the E
2
PROM array (store and recall functions).
PIN NAMES
Symbol
A
0
–A
8
I/O
0
–I/O
7
WE
CE
OE
NE
V
CC
V
SS
NC
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
Nonvolatile Enable
+5V
Ground
No Connect
3825 PGM T01
FUNCTIONAL DIAGRAM
VCC SENSE
EEPROM ARRAY
A3–A6
ROW
SELECT
CE
OE
WE
NE
A0–A2
A7–A8
COLUMN
SELECT
&
I/OS
CONTROL
LOGIC
I/O0–I/O7
ST
O
R
E
512 x 8
SRAM
ARRAY
R
EC
AL
L
3825 FHD F01
2
X20C04
DEVICE OPERATION
The
CE, OE, WE
and
NE
inputs control the X20C04
operation. The X20C04 byte-wide NOVRAM uses a
2-line control architecture to eliminate bus contention in
a system environment. The I/O bus will be in a high
impedance state when either
OE
or
CE
is HIGH, or
when
NE
is LOW.
RAM Operations
RAM read and write operations are performed as they
would be with any static RAM. A read operation requires
CE
and
OE
to be LOW with
WE
and
NE
HIGH. A write
operation requires
CE
and
WE
to be LOW with
NE
HIGH. There is no limit to the number of read or write
operations performed to the RAM portion of the X20C04.
Nonvolatile Operations
With
NE
LOW, recall operation is performed in the same
manner as RAM read operation. A recall operation
causes the entire contents of the E
2
PROM to be written
into the RAM array. The time required for the operation
to complete is 5µs or less. A store operation causes the
entire contents of the RAM array to be stored in the
nonvolatile E
2
PROM. The time for the operation to
complete is 5ms or less.
Power-Up Recall
Upon power-up (V
CC
), the X20C04 performs an auto-
matic array recall. When V
CC
minimum is reached, the
recall is initiated, regardless of the state of
CE, OE, WE
and
NE.
Write Protection
The X20C04 has five write protect features that are
employed to protect the contents of both the nonvolatile
memory and the RAM.
• V
CC
Sense—All functions are inhibited when V
CC
is
≤
3.5V.
• A RAM write is required before a Store Cycle is
initiated.
• Write Inhibit—Holding either
OE
LOW,
WE
HIGH,
CE
HIGH, or
NE
HIGH during power-up and power-
down will prevent an inadvertent store operation.
• Noise Protection—A combined
WE, NE, OE
and
CE
pulse of less than 20ns will not initiate a Store
Cycle.
• Noise Protection—A combined
WE, NE, OE
and
CE
pulse of less than 20ns will not initiate a recall
cycle.
SYMBOL TABLE
WAVEFORM
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
3
X20C04
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to V
SS .......................................
–1V to +7V
D.C. Output Current ........................................... 10mA
Lead Temperature (Soldering, 10 seconds) ..... 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Military
Min.
0°C
–40°C
–55°C
Max.
+70°C
+85°C
+125°C
3825 PGM T02.1
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Supply Voltage
X20C04
Limits
5V
±10%
3825 PGM T03
D.C. OPERATING CHARACTERISTICS
(Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
l
CC1
Parameter
V
CC
Current (Active)
Min.
Max.
100
Units
mA
Test Conditions
NE
=
WE
= V
IH
,
CE
=
OE
= V
IL
Address Inputs = 0.4V/2.4V levels
@ f = 5MHz. All I/Os = Open
All Inputs = V
IH
All I/Os = Open
CE
= V
IH
All Other Inputs = V
IH
, All I/Os = Open
All Inputs = V
CC
– 0.3V
All I/Os = Open
V
IN
= V
SS
to V
CC
V
OUT
= V
SS
to V
CC
,
CE
= V
IH
I
CC2
I
SB1
I
SB2
I
LI
I
LO
V
IL(1)
V
IH(1)
V
OL
V
OH
V
CC
Current During Store
V
CC
Standby Current
(TTL Input)
V
CC
Standby Current
(CMOS Input)
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
10
10
250
10
10
0.8
V
CC
+ 0.5
0.4
mA
mA
µA
µA
µA
V
V
V
V
–1
2
2.4
I
OL
= 2.1mA
I
OH
= –400µA
3825 PGM T04.3
POWER-UP TIMING
Symbol
t
PUR(2)
t
PUW(2)
Parameter
Power-Up to RAM Operation
Power-Up to Nonvolatile Operation
Max.
100
5
Units
µs
ms
3825 PGM T05
CAPACITANCE
T
A
= +25°C, F = 1MHz, V
CC
= 5V.
Symbol
C
I/O(2)
C
IN(2)
Test
Input/Output Capacitance
Input Capacitance
Max.
10
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
3825 PGM T06.1
Notes:
(1) V
IL
min. and V
IH
max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
4
X20C04
ENDURANCE AND DATA RETENTION
Parameter
Endurance
Store Cycles
Data Retention
MODE SELECTION
CE
H
L
L
L
L
L
L
L
L
WE
X
H
L
L
H
L
H
L
H
NE
X
H
H
H
L
L
H
L
L
OE
X
L
H
H
L
H
H
L
H
Mode
Not Selected
Read RAM
Write “1” RAM
Write “0” RAM
Array Recall
Nonvolatile Storing
Output Disabled
Not Allowed
No Operation
I/O
Output High Z
Output Data
Input Data High
Input Data Low
Output High Z
Output High Z
Output High Z
Output High Z
Output High Z
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Active
3825 PGM T09.1
Min.
100,000
1,000,000
100
Units
Data Changes Per Bit
Store Cycles
Years
3825 PGM T07.1
EQUIVALENT A.C. LOAD CIRCUIT
5V
1.92KΩ
OUTPUT
1.37KΩ
100pF
A.C. CONDITIONS OF TEST
Input Pulse Levels
Input Rise and
Fall Times
Input and Output
Timing Levels
0V to 3V
10ns
1.5V
3825 PGM T08.2
3825 FHD F04.1
5
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