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662M-03T

Description
PLL Based Clock Driver, 662 Series, 1 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, SOIC-8
Categorylogic    logic   
File Size120KB,7 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

662M-03T Overview

PLL Based Clock Driver, 662 Series, 1 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, SOIC-8

662M-03T Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeSOIC
package instruction0.150 INCH, SOIC-8
Contacts8
Reach Compliance Code_compli
series662
Input adjustmentSTANDARD
JESD-30 codeR-PDSO-G8
JESD-609 codee0
length4.9 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Humidity sensitivity level1
Number of functions1
Number of inverted outputs
Number of terminals8
Actual output times1
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Certification statusNot Qualified
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
width3.9 mm
Base Number Matches1
DATASHEET
HDTV AUDIO/VIDEO CLOCK SOURCE
Description
The ICS662-03 provides synchronous clock generation for
audio sampling clock rates derived from an HDTV stream.
The device uses the latest PLL technology to provide
superior phase noise and long term jitter performance. The
device also supports a 27 MHz output clock for video
MPEG applications from an HDTV reference clock.
Please contact ICS if you have a requirement for an input
and output frequency not included here.
ICS662-03
Features
Packaged in 8-pin SOIC
Available in Pb (lead) free package
HDTV clock input
Low phase noise
Exact (0 ppm) multiplication ratios
Support for 256 and 384 times sampling rate
Supports 27 MHz output for video (MPEG)
Block Diagram
VDD
SEL3:0
Control
Circuitry
PLL
Clock
Synthesis
CLK
REF_IN
GND
IDT™ / ICS™
HDTV AUDIO/VIDEO CLOCK SOURCE
1
ICS662-03
REV E 101807

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Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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