The SCLK output was not adjusted overnight.
The Verilog program has been written. The SCLK output is normal during simulation, but ILA does not know why SCLK always has no output. There was a version ...
[i=s] This post was last edited by shihuntaotie on 2019-1-9 21:39 [/i] [font=宋体][size=4] Read all sensor data of the kit according to the evaluation plan, and still use the online IDE for programming....
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