FTS1MX8-XXX
1MX8
organised
2x512Kx8 SRAM
FEATURES
Access Times 17, 20, 25, 35, 45, 55ns
Revolutionary, Center Power/Ground Pinout
Packaging:
• 32 pin, Hermetic Ceramic DIP (D)
• 36 lead Ceramic SOJ (Package S)
• 36 lead Ceramic Flatpack (Package F)
Organised as two banks of 512Kx8
Commercial, Industrial and Military Temperature Ranges
5 Volt Power Supply
Low Power CMOS
TTL Compatible Inputs and Outputs
PIN CONFIGURATION FOR
FTS1MX8-XSX
AND
FTS1MX8-XFX
36 CSOJ
36 FLATPACK
PIN CONFIGURATION FOR
FTS1MX8-XDX
32 DIP
TOP VIEW
NC
A18
A17
A16
A15
OE#
I/O7
I/O6
GND
V
CC
I/O5
I/O4
A14
A13
A12
A11
A10
CS2#
TOP VIEW
A0
A1
A2
A3
A4
CS1#
I/O0
I/O1
V
CC
GND
I/O2
I/O3
WE#
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
A17
WE#
A13
A8
A9
A11
CS2#
A10
CS1#
I/O7
I/O6
I/O5
I/O4
I/O3
Pin Description
A0-18
I/O0-7
CS1-2#
OE#
WE#
V
CC
GND
Address Inputs
Data Input/Output
Chip Selects
Output Enable
Write Enable
+5.0V Power
Ground
I/O0-7
WE#
OE#
A0-18
Pin Description
A0-18
I/O0-7
CS1-2#
WE#
V
CC
GND
Address Inputs
Data Input/Output
Chip Selects
Write Enable
+5.0V Power
Ground
Block Diagram
Block Diagram
I/O0-7
WE#
A0-18
512K x 8
512K x 8
512K x 8
512K x 8
NOTE:
1. CS1# and CS2# are used to select the lower and upper 512Kx8 of the device. CS1# and CS2# must not be enabled at the same time.
July 2007
Rev. 1
CS1#
(1)
CS2#
(1)
CS
1#
(1)
CS
2#
(1)
1
FTS1MX8-XXX
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
Symbol
T
A
T
STG
V
G
T
J
V
CC
-0.5
Min
-55
-65
-0.5
Max
+125
+150
V
CC
+0.5
150
7.0
Unit
°C
°C
V
°C
V
TRUTH TABLE
CS#
H
L
L
L
OE#
X
L
X
H
WE#
X
H
L
H
Mode
Standby
Read
Write
Out Disable
Data I/O
High Z
Data Out
Data In
High Z
Power
Standby
Active
Active
Active
NOTE: OE# is internally tied to the GND and not accessible on the WS1M8-XCXX.
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
Symbol
V
CC
V
IH
V
IL
T
A
Min
4.5
2.2
-0.3
-55
Max
5.5
V
CC
+ 0.3
+0.8
+125
Unit
V
V
V
°C
Parameter
Input capacitance
Output capicitance
CAPACITANCE
T
A
= +25°C
Symbol
C
IN
C
OUT
Condition
V
IN
= 0V, f = 1.0MHz
V
OUT
= 0V, f = 1.0MHz
Max
20
20
Unit
pF
pF
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
V
CC
= 5.0V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Current
Output Low Voltage
Output High Voltage
Sym
I
LI
I
LO
1
1
Conditions
V
CC
= 5.5, V
IN
= GND to V
CC
CS# = V
IH
, OE# = V
IH
, V
OUT
= GND to V
CC
CS# = V
IL
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
CS# = V
IH
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
I
OL
= 6mA
I
OH
= -4.0mA
Min
Max
10
10
180
40
0.4
Units
μA
μA
mA
mA
V
V
I
CC
I
SB
1
V
OL
V
OH
2.4
NOTE: DC test conditions: V
IH
= V
CC
-0.3V , V
IL
= 0.3V
1. OE# is internally tied to the GND and not accessible on the WS1M8-XCXX.
July 2007
Rev. 1
2
FTS1MX8-XXX
AC CHARACTERISTICS
V
CC
= 5.0V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Symbol
t
RC
t
AA
t
OH
t
ACS
t
OE
2
t
CLZ
1
t
OLZ
2
t
CHZ
1
t
OHZ
2
-17
Min
17
0
17
9
2
0
9
9
2
0
10
10
Max
17
0
20
10
2
0
12
12
Min
20
-20
Max
20
0
25
12
4
0
15
15
Min
25
-25
Max
25
0
35
25
4
0
20
20
Min
35
-35
Max
35
0
45
25
4
0
20
20
Min
45
-45
Max
45
0
55
25
Min
55
-55
Max
55
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
2. OE# is internally tied to the GND and not accessible on the WS1M8-XCXX.
AC CHARACTERISTICS
V
CC
= 5.0V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
Symbol
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW
1
t
WHZ
1
t
DH
17
14
14
9
14
0
0
2
9
0
0
-17
20
14
14
10
14
0
0
3
9
0
-20
25
15
15
10
15
0
0
4
10
0
-25
35
25
25
20
25
0
0
4
15
0
-35
45
35
35
25
35
0
5
5
15
0
-45
55
50
50
25
40
0
5
5
25
-55
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
AC TEST CIRCUIT
I
OL
Current Source
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
V
Z
Typ
VIL = 0, VIH = 3.0
5
1.5
1.5
Unit
V
ns
V
V
D.U.T.
C
eff
= 50 pf
≈
1.5V
(Bipolar Supply)
I
OH
Current Source
Notes:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75
Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
July 2007
Rev. 1
3
FTS1MX8-XXX
TIMING WAVEFORM – READ CYCLE
t
RC
ADDRESS
t
RC
ADDRESS
t
AA
CS#
t
AA
t
OH
DATA I/O
PREVIOUS DATA VALID
DATA VALID
t
ACS
t
CLZ
OE#
t
CHZ
READ CYCLE 1 (CS# = OE# = V
IL
, WE# = V
IH
)
t
OE
t
OLZ
DATA I/O
HIGH IMPEDANCE
t
OHZ
DATA VALID
READ CYCLE 2 (WE# = V
IH
)
NOTE: OE# is internally tied to the GND and not accessible on the WS1M8-XCXX.
WRITE CYCLE – WE# CONTROLLED
t
WC
ADDRESS
t
AW
t
CW
CS#
t
AS
WE#
t
WHZ
DATA I/O
t
DW
t
WP
t
OW
t
DH
t
AH
DATA VALID
WRITE CYCLE 1, WE# CONTROLLED
WRITE CYCLE – CS# CONTROLLED
t
WC
ADDRESS
t
AS
CS#
t
AW
t
CW
t
AH
t
WP
WE#
t
DW
DATA I/O
DATA VALID
t
DH
WRITE CYCLE 2, CS# CONTROLLED
July 2007
Rev. 1
4
FTS1MX8-XXX
S-
36 LEAD, CERAMIC SOJ
23.37 (0.920) ± 0.25 (0.010)
0.20 (0.008)
± 0.05 (0.002)
4.76 (0.184)
MIN
0.89 (0.035)
Radius TYP
11.3 (0.446)
± 0.2 (0.009)
9.55 (0.376) ± 0.25 (0.010)
1.27 (0.050) ± 0.25 (0.010)FP
PIN 1 IDENTIFIER
1.27 (0.050) TYP
21.59 (0.850) TYP
0.43 (0.017)
± 0.05 (0.002)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
F-
36 LEAD, CERAMIC FLAT PACK
23.37 (0.920)
± 0.25 (0.010)
3.18 (0.125)
MIN
PIN 1
IDENTIFIER
12.95 (0.510)
± 0.13 (0.005)
12.7 (0.500)
± 0.5 (0.020)
5.1 (0.200)
± 0.25 (0.010)
0.43 (0.017)
± 0.05 (0.002)
32.64 (1.285) TYP
0.127 (0.005)
± 0.05 (0.002)
1.27 (0.050) TYP
21.59 (0.850) TYP
38.1 (1.50) ± 0.4 (0.015)
3.8 (0.150)
TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
July 2007
Rev. 1
5
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