Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC5607B
Rev. 7, 05/2013
MPC5607B
100 LQFP
14 mm x 14 mm
144 LQFP
20 mm x 20 mm
MPC5607B Microcontroller
Data Sheet
•
Single issue, 32-bit CPU core complex (e200z0h)
— Compliant with the Power Architecture
®
technology
embedded category
— Enhanced instruction set allowing variable length
encoding (VLE) for code size footprint reduction.
With the optional encoding of mixed 16-bit and
32-bit instructions, it is possible to achieve
significant code size footprint reduction.
Up to 1.5 MB on-chip code flash memory supported with
the flash memory controller and ECC
64 (4 × 16) KB on-chip data flash memory with ECC
Up to 96 KB on-chip SRAM with ECC
Memory protection unit (MPU) with 8 region descriptors
and 32-byte region granularity on certain family
members (Refer to
Table 1
for details.)
Interrupt controller (INTC) capable of handling 204
selectable-priority interrupt sources
Frequency modulated phase-locked loop (FMPLL)
Crossbar switch architecture for concurrent access to
peripherals, Flash, or RAM from multiple bus masters
16-channel eDMA controller with multiple transfer
request sources using DMA multiplexer
Boot assist module (BAM) supports internal Flash
programming via a serial link (CAN or SCI)
Timer supports I/O channels providing a range of 16-bit
input capture, output compare, and pulse width
modulation functions (eMIOS)
2 analog-to-digital converters (ADC): one 10-bit and one
12-bit
Cross Trigger Unit to enable synchronization of ADC
conversions with a timer event from the eMIOS or PIT
Up to 6 serial peripheral interface (DSPI) modules
Up to 10 serial communication interface (LINFlex)
modules
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176 LQFP
24 mm x 24 mm
208 MAPBGA
17 mm x 17 mm
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•
•
•
•
•
•
•
•
•
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Up to 6 enhanced full CAN (FlexCAN) modules with
configurable buffers
1 inter-integrated circuit (I
2
C) interface module
Up to 149 configurable general purpose pins supporting
input and output operations (package dependent)
Real-Time Counter (RTC)
— Clock source from internal 128 kHz or 16 MHz
oscillator supporting autonomous wakeup with 1 ms
resolution with maximum timeout of 2 seconds
— Optional support for RTC with clock source from
external 32 kHz crystal oscillator, supporting
wakeup with 1 sec resolution and maximum timeout
of 1 hour
Up to 8 periodic interrupt timers (PIT) with 32-bit
counter resolution
Nexus development interface (NDI) per IEEE-ISTO
5001-2003 Class Two Plus
Device/board boundary scan testing supported per Joint
Test Action Group (JTAG) of IEEE (IEEE 1149.1)
On-chip voltage regulator (VREG) for regulation of input
supply for all internal levels
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© Freescale Semiconductor, Inc., 2010-2013. All rights reserved.
Table of Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Document overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . .8
3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.2 Pad configuration during reset phases . . . . . . . . . . . . .11
3.3 Pad configuration during standby mode exit . . . . . . . . .12
3.4 Voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.5 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.7 Functional port pins . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.8 Nexus 2+ pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
4.1 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .34
4.2 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
4.2.1 NVUSRO[PAD3V5V] field description . . . . . . . .34
4.2.2 NVUSRO[OSCILLATOR_MARGIN] field
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.2.3 NVUSRO[WATCHDOG_EN] field description . .35
4.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .35
4.4 Recommended operating conditions . . . . . . . . . . . . . .36
4.5 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .39
4.5.1 External ballast resistor recommendations . . . .39
4.5.2 Package thermal characteristics . . . . . . . . . . . .39
4.5.3 Power considerations. . . . . . . . . . . . . . . . . . . . .40
4.6 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . .41
4.6.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.6.2 I/O input DC characteristics . . . . . . . . . . . . . . . .41
4.6.3 I/O output DC characteristics. . . . . . . . . . . . . . .42
4.6.4 Output pin transition times . . . . . . . . . . . . . . . . .45
4.6.5 I/O pad current specification . . . . . . . . . . . . . . .45
4.7 RESET electrical characteristics. . . . . . . . . . . . . . . . . .53
4.8 Power management electrical characteristics. . . . . . . .56
4.8.1 Voltage regulator electrical characteristics . . . .56
4.8.2 Low voltage detector electrical characteristics .58
4.9 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.10 Flash memory electrical characteristics . . . . . . . . . . . 61
4.10.1 Program/erase characteristics . . . . . . . . . . . . . 61
4.10.2 Flash power supply DC characteristics . . . . . . 62
4.10.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . 63
4.11 Electromagnetic compatibility (EMC) characteristics. . 63
4.11.1 Designing hardened software to avoid
noise problems . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.11.2 Electromagnetic interference (EMI) . . . . . . . . . 64
4.11.3 Absolute maximum ratings (electrical sensitivity)64
4.12 Fast external crystal oscillator (4 to 16 MHz)
electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 65
4.13 Slow external crystal oscillator (32 kHz)
electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 68
4.14 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 70
4.15 Fast internal RC oscillator (16 MHz)
electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 71
4.16 Slow internal RC oscillator (128 kHz)
electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 72
4.17 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 73
4.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.17.2 Input impedance and ADC accuracy . . . . . . . . 74
4.17.3 ADC electrical characteristics . . . . . . . . . . . . . 79
4.18 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.18.1 Current consumption . . . . . . . . . . . . . . . . . . . . 84
4.18.2 DSPI characteristics. . . . . . . . . . . . . . . . . . . . . 86
4.18.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . 92
4.18.4 JTAG characteristics. . . . . . . . . . . . . . . . . . . . . 93
Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 95
5.1.1 176 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.1.2 144 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.1.3 100 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.1.4 208 MAPBGA. . . . . . . . . . . . . . . . . . . . . . . . . 103
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
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5
6
7
MPC5607B Microcontroller Data Sheet, Rev. 7
2
Freescale Semiconductor
Introduction
1
1.1
Introduction
Document overview
This document describes the features of the family and options available within the family members, and highlights important
electrical and physical characteristics of the device.
1.2
Description
This family of 32-bit system-on-chip (SoC) microcontrollers is the latest achievement in integrated automotive application
controllers. It belongs to an expanding family of automotive-focused products designed to address the next wave of body
electronics applications within the vehicle.
The advanced and cost-efficient e200z0h host processor core of this automotive controller family complies with the
Power Architecture technology and only implements the VLE (variable-length encoding) APU (Auxiliary Processor Unit),
providing improved code density. It operates at speeds of up to 64 MHz and offers high performance processing optimized for
low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and
is supported with software drivers, operating systems and configuration code to assist with users implementations.
Table 1. MPC5607B family comparison
1
Feature
CPU
Execution speed
2
Code flash memory
Data flash memory
SRAM
MPU
eDMA
10-bit ADC
dedicated
3
shared with 12-bit ADC
12-bit ADC
dedicated
4
shared with 10-bit ADC
Total timer I/O
5
eMIOS
Counter / OPWM / ICOC
6
O(I)PWM / OPWFMB /
OPWMCB / ICOC
7
O(I)PWM / ICOC
8
OPWM / ICOC
9
SCI (LINFlex)
SPI (DSPI)
7 ch
13 ch
4
3
5
6
8
5
6
37 ch,
16-bit
7 ch
15 ch
29 ch
64 KB
768 KB
MPC5605B
MPC5606B
e200z0h
Up to 64 MHz
1 MB
64 (4
16) KB
80 KB
8-entry
16 ch
Yes
15 ch
19 ch
Yes
5 ch
19 ch
64 ch, 16-bit
10 ch
7 ch
14 ch
33 ch
10
29 ch
96 KB
1.5 MB
MPC5607B
MPC5607B Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
3
Introduction
Table 1. MPC5607B family comparison
1
(continued)
Feature
CAN (FlexCAN)
I
2
C
32 KHz oscillator
GPIO
10
Debug
Package
1
MPC5605B
MPC5606B
6
1
Yes
MPC5607B
77
121
149
JTAG
121
149
N2+
100
LQFP
144
LQFP
176
LQFP
144
LQFP
176
LQFP
176
LQFP
208 MAP
BGA
11
Feature set dependent on selected peripheral multiplexing; table shows example
2
Based on 125
C
ambient operating temperature
3
Not shared with 12-bit ADC, but possibly shared with other alternate functions
4
Not shared with 10-bit ADC, but possibly shared with other alternate functions
5
See the eMIOS section of the chip reference manual for information on the channel configuration and functions.
6
Each channel supports a range of modes including Modulus counters, PWM generation, Input Capture, Output
Compare.
7
Each channel supports a range of modes including PWM generation with dead time, Input Capture, Output
Compare.
8
Each channel supports a range of modes including PWM generation, Input Capture, Output Compare, Period and
Pulse width measurement.
9
Each channel supports a range of modes including PWM generation, Input Capture, and Output Compare.
10
Maximum I/O count based on multiplexing with peripherals
11
208 MAPBGA available only as development package for Nexus2+
MPC5607B Microcontroller Data Sheet, Rev. 7
4
Freescale Semiconductor
Block diagram
2
Block diagram
JTAG
JTAG Port
Nexus Port
Nexus
NMI
SIUL
Voltage
Regulator
NMI
Interrupt requests
from peripheral
blocks
INTC
Clocks
FMPLL
CMU
eDMA
(Master)
64-bit 2
3 Crossbar Switch
Instructions
e200z0h
(Master)
Data
Nexus 2+
(Master)
SRAM
Controller
MPU
SRAM
96 KB
Code Flash
1.5 MB
Data Flash
64 KB
Figure 1
shows a top-level block diagram of the MPC5607B.
Flash
Controller
(Slave)
(Slave)
Interrupt
request with
wakeup
functionality
WKPU
(Slave)
MPU
Registers
RTC
STM
SWT
ECSM
PIT
MC_RGM
MC_CGM
MC_ME MC_PCU
BAM
SSCM
Peripheral Bridge
Interrupt
Request
SIUL
Reset Control
External
Interrupt
Request
IMUX
GPIO &
Pad Control
19 ch 10-bit/12-bit
ADC
29 ch 10-bit
ADC
CTU
64 ch
eMIOS
10
LINFlex
6
DSPI
I
2
C
6
FlexCAN
5 ch 12-bit
ADC
I/O
Legend:
ADC
BAM
CMU
CTU
DSPI
ECSM
eDMA
eMIOS
Flash
FlexCAN
FMPLL
GPIO
I
2
C
IMUX
INTC
JTAG
LINFlex
...
...
...
...
...
Analog-to-Digital Converter
Boot Assist Module
Clock Monitor Unit
Cross Triggering Unit
Deserial Serial Peripheral Interface
Error Correction Status Module
Enhanced Direct Memory Access
Enhanced Modular Input Output System
Flash memory
Controller Area Network
Frequency-Modulated Phase-Locked Loop
General-purpose input/output
Inter-Integrated Circuit bus
Internal Multiplexer
Interrupt Controller
JTAG controller
Serial Communication Interface (LIN support)
MC_CGM
MC_ME
MC_PCU
MC_RGM
MPU
NMI
PIT
RTC
SIUL
SRAM
SSCM
STM
SWT
VREG
WKPU
XBAR
Clock Generation Module
Mode Entry Module
Power Control Unit
Reset Generation Module
Memory Protection Unit
Non-Maskable Interrupt
Periodic Interrupt Timer
Real-Time Clock
System Integration Unit Lite
Static Random-Access Memory
System Status Configuration Module
System Timer Module
Software Watchdog Timer
Voltage regulator
Wakeup Unit
Crossbar switch
Figure 1. MPC5607B block diagram
MPC5607B Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
5
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