FS6131_08 datasheet, PDF - EEWORLD Datasheet

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FS6131_08: DescriptionPLL FREQUENCY SYNTHESIZER, 27 MHz, PDSO16; Categoryaccessories; File Size486KB，44 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn

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FS6131_08 Overview

PLL FREQUENCY SYNTHESIZER, 27 MHz, PDSO16

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FS6131

Programmable Line Lock Clock Generator IC

1.0 Key Features

•

Complete programmable control via I

C™-bus

Selectable CMOS or PECL compatible outputs

External feedback loop capability allows genlocking

Tunable VCXO loop for jitter attenuation

2.0 General Description

The FS6131-01 is a monolithic CMOS clock generator/regenerator IC designed to minimize cost and component count in a variety of

electronic systems. Via the I C-bus interface, the FS6131-01 can be adapted to many clock generation requirements.

The ability to tune the on-board voltage-controlled crystal oscillator (VCXO), the length of the reference and feed-back dividers, their

granularity, and the flexibility of the post divider make the FS6131-01 the most flexible stand-alone phase-locked loop (PLL) clock

generator available.

3.0 Applications

•

Frequency synthesis

Line-locked and genlock applications

Clock multiplication

Telecom jitter attenuation

SCL

SDA

ADDR

VSS

XIN

XOUT

XTUNE

VDD

CLKN

CLKP

VDD

FBK

REF

VSS

EXTLF

LOCK/IPRG

FS6131

16-pin 0.150" SOIC

Figure 1: Pin Configuration

May 2008 – Rev. 4

Publication Order Number:

FS6131/D

FS6131

4.0 Functional Block Description

4.1 Main Loop PLL

The main loop phase locked loop (ML-PLL) is a standard phase- and frequency- locked loop architecture. As shown in

Error!

Reference source not found.,

the ML-PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an

internal loop filter, a voltage-controlled oscillator (VCO), a feedback divider, and a post divider.

During operation, the reference frequency (f

REF

), generated by either the on-board crystal oscillator or an external frequency source, is

first reduced by the reference divider. The integer value that the frequency is divided by is called the modulus, and is denoted as N

for

the reference divider. The divided reference is then fed into the PFD.

The PFD controls the frequency of the VCO (f

VCO

) through the charge pump and loop filter. The VCO provides a high-speed, low noise,

continuously variable frequency clock source for the ML-PLL. The output of the VCO is fed back to the PFD through the feedback

divider (the modulus is denoted by N

) to close the loop.

The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at

the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is

VCO

REF

If the VCO frequency is used as the PLL output frequency (f

CLK

) then the basic PLL equation can be rewritten as

⎛

⎞

CLK

REF

⎜

⎟

⎜

⎟

⎝

⎠

4.1.1. Reference Divider

The reference divider is designed for low phase jitter. The divider accepts either the output of either the crystal loop (the VCXO output)

or an external reference frequency, and provides a divided-down frequency to the PFD. The reference divider is a 12-bit divider, and

can be programmed for any modulus from 1 to 4095. See both Table 3 and Table 8 for additional programming information.

4.1.2. Feedback Divider

The feedback divider is based on a dual-modulus pre-scaler technique. The technique allows the same granularity as a fully

programmable feedback divider, while still allowing the programmable portion to operate at low speed. A high-speed pre-divider (also

called a prescaler) is placed between the VCO and the programmable feedback divider because of the high speeds at which the VCO

can operate. The dual-modulus technique insures reliable operation at any speed that the VCO can achieve and reduces the overall

power consumption of the divider.

For example, a fixed divide-by-eight could be used in the feedback divider. Unfortunately, a divide-by-eight would limit the effective

modulus of the feedback divider path to multiples of eight. The limitation would restrict the ability of the PLL to achieve a desired input-

frequency-to-output frequency ratio without making both the reference and feedback divider values comparatively large. Large divider

moduli are generally undesirable due to increased phase jitter.

Rev. 4 | Page 3 of 44 | www.onsemi.com

FS6131_08 Related Products

	FS6131_08	FS6131	FS6131-01G	FS6131-01
Description	PLL FREQUENCY SYNTHESIZER, 27 MHz, PDSO16	PLL FREQUENCY SYNTHESIZER, 27 MHz, PDSO16	PLL FREQUENCY SYNTHESIZER, 27 MHz, PDSO16	PLL FREQUENCY SYNTHESIZER, 27 MHz, PDSO16

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