Section I. Arria GX Device Data Sheet
This section provides designers with the data sheet specifications for Arria
®
GX
devices. They contain feature definitions of the transceivers, internal architecture,
configuration, and JTAG boundary-scan testing information, DC operating
conditions, AC timing parameters, a reference to power consumption, and ordering
information for Arria GX devices.
This section includes the following chapters:
■
■
■
■
■
Chapter 1, Arria GX Device Family Overview
Chapter 2, Arria GX Architecture
Chapter 3, Configuration and Testing
Chapter 4, DC and Switching Characteristics
Chapter 5, Reference and Ordering Information
Revision History
Refer to each chapter for its own specific revision history. For information about when
each chapter was updated, refer to the Chapter Revision Dates section, which appears
in the full handbook.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
I–2
Section I: Arria GX Device Data Sheet
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
1. Arria GX Device Family Overview
AGX51001-2.0
Introduction
The Arria
®
GX family of devices combines 3.125 Gbps serial transceivers with reliable
packaging technology and a proven logic array. Arria GX devices include 4 to 12
high-speed transceiver channels, each incorporating clock data recovery (CDR)
technology and embedded SERDES circuitry designed to support PCI-Express,
Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO protocols, along with
the ability to develop proprietary, serial-based IP using its Basic mode. The
transceivers build upon the success of the Stratix
®
II GX family. The Arria GX FPGA
technology offers a 1.2-V logic array with the right level of performance and
dependability needed to support these mainstream protocols.
Features
The key features of Arria GX devices include:
■
Transceiver block features
■
■
High-speed serial transceiver channels with CDR support up to 3.125 Gbps.
Devices available with 4, 8, or 12 high-speed full-duplex serial transceiver
channels
Support for the following CDR-based bus standards—PCI Express, Gigabit
Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO, along with the ability to
develop proprietary, serial-based IP using its Basic mode
Individual transmitter and receiver channel power-down capability for
reduced power consumption during non-operation
1.2- and 1.5-V pseudo current mode logic (PCML) support on transmitter
output buffers
Receiver indicator for loss of signal (available only in PCI Express [PIPE]
mode)
Hot socketing feature for hot plug-in or hot swap and power sequencing
support without the use of external devices
Dedicated circuitry that is compliant with PIPE, XAUI, Gigabit Ethernet, Serial
Digital Interface (SDI), and Serial RapidIO
8B/10B encoder/decoder performs 8-bit to 10-bit encoding and 10-bit to 8-bit
decoding
Phase compensation FIFO buffer performs clock domain translation between
the transceiver block and the logic array
Channel aligner compliant with XAUI
■
■
■
■
■
■
■
■
■
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
1–2
Chapter 1: Arria GX Device Family Overview
Features
■
Main device features:
■
TriMatrix memory consisting of three RAM block sizes to implement true
dual-port memory and first-in first-out (FIFO) buffers with performance up to
380 MHz
Up to 16 global clock networks with up to 32 regional clock networks per
device
High-speed DSP blocks provide dedicated implementation of multipliers,
multiply-accumulate functions, and finite impulse response (FIR) filters
Up to four enhanced phase-locked loops (PLLs) per device provide spread
spectrum, programmable bandwidth, clock switch-over, and advanced
multiplication and phase shifting
Support for numerous single-ended and differential I/O standards
High-speed source-synchronous differential I/O support on up to 47 channels
Support for source-synchronous bus standards, including SPI-4 Phase 2
(POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1
Support for high-speed external memory including DDR and DDR2 SDRAM,
and SDR SDRAM
Support for multiple intellectual property megafunctions from Altera
®
MegaCore
®
functions and Altera Megafunction Partners Program (AMPP
SM
)
Support for remote configuration updates
■
■
■
■
■
■
■
■
■
Table 1–1
lists Arria GX device features for FineLine BGA (FBGA) with flip chip
packages.
Table 1–1.
Arria GX Device Features (Part 1 of 2)
EP1AGX20C
Feature
C
Package
484-pin,
780-pin
(Flip chip)
8,632
21,580
C
484-pin
(Flip chip)
D
780-pin
(Flip chip)
C
484-pin
(Flip chip)
D
780-pin,
1152-pin
(Flip chip)
13,408
33,520
20,064
50,160
24,040
60,100
36,088
90,220
C
484-pin
D
780-pin
E
E
1152-pin
(Flip chip)
1152-pin
(Flip chip) (Flip chip) (Flip chip)
EP1AGX35C/D
EP1AGX50C/D
EP1AGX60C/D/E
EP1AGX90E
ALMs
Equivalent
logic
elements
(LEs)
Transceiver
channels
Transceiver
data rate
Source-
synchronous
receive
channels
4
600 Mbps
to 3.125
Gbps
31
4
8
4
8
4
8
12
12
600 Mbps
to 3.125
Gbps
47
600 Mbps to 3.125
Gbps
600 Mbps to 3.125
Gbps
600 Mbps to 3.125 Gbps
31
31
31
31, 42
31
31
42
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 1: Arria GX Device Family Overview
Features
1–3
Table 1–1.
Arria GX Device Features (Part 2 of 2)
EP1AGX20C
Feature
C
Source-
synchronous
transmit
channels
M512 RAM
blocks
(32 × 18 bits)
M4K RAM
blocks
(128 × 36
bits)
M-RAM
blocks
(4096 × 144
bits)
Total RAM
bits
Embedded
multipliers
(18 × 18)
DSP blocks
PLLs
Maximum
user I/O pins
C
D
C
D
C
D
E
E
EP1AGX35C/D
EP1AGX50C/D
EP1AGX60C/D/E
EP1AGX90E
29
29
29
29
29, 42
29
29
42
45
166
197
313
326
478
118
140
242
252
400
1
1
2
2
4
1,229,184
1,348,416
2,475,072
2,528,640
4,477,824
40
10
4
230, 341
230
56
14
4
341
4
229
104
26
4, 8
350, 514
229
4
128
32
8
350
514
176
44
8
538
Arria GX devices are available in space-saving FBGA packages (refer to
Table 1–2).
All
Arria GX devices support vertical migration within the same package. With vertical
migration support, designers can migrate to devices whose dedicated pins,
configuration pins, and power pins are the same for a given package across device
densities. For I/O pin migration across densities, the designer must cross-reference
the available I/O pins with the device pin-outs for all planned densities of a given
package type to identify which I/O pins are migratable.
Table 1–2.
Arria GX Package Options (Pin Counts and Transceiver Channels) (Part 1 of 2)
Source-Synchronous Channels
Device
Transceiver
Channels
4
4
4
4
8
8
Receive
31
31
31
31
31
31, 42
Transmit
29
29
29
29
29
29, 42
Maximum User I/O Pin Count
484-Pin FBGA
(23 mm)
230
230
229
229
—
—
780-Pin FBGA
(29 mm)
341
—
—
—
341
350
1152-Pin
FBGA
(35 mm)
—
—
—
—
—
514
EP1AGX20C
EP1AGX35C
EP1AGX50C
EP1AGX60C
EP1AGX35D
EP1AGX50D
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
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