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Audio, Dual-Matched
NPN Transistor
SSM2212
FEATURES
Very low voltage noise: 1 nV/√Hz maximum @ 100 Hz
Excellent current gain match: 0.5%
Low offset voltage (V
OS
): 200 μV maximum
Outstanding offset voltage drift: 0.03 μV/°C
High gain bandwidth product: 200 MHz
PIN CONFIGURATION
C
1 1
B
1 2
E
1 3
NIC
4
8
7
6
C
2
B
2
E
2
09043-001
SSM2212
5
NIC
NIC = NO INTERNAL CONNECTION
Figure 1. 8-Lead SOIC_N
GENERAL DESCRIPTION
The SSM2212 is a dual, NPN-matched transistor pair that is
specifically designed to meet the requirements of ultralow noise
audio systems.
With its extremely low input base spreading resistance (rbb' is
typically 28 Ω) and high current gain (h
FE
typically exceeds 600
at I
C
= 1 mA), the SSM2212 can achieve outstanding signal-to-
noise ratios. The high current gain results in superior
performance compared to systems incorporating commercially
available monolithic amplifiers.
Excellent matching of the current gain (Δh
FE
) to about 0.5% and
low V
OS
of less than 10 μV typical make the SSM2212 ideal for
symmetrically balanced designs, which reduce high-order
amplifier harmonic distortion.
Stability of the matching parameters is guaranteed by protection
diodes across the base-emitter junction. These diodes prevent
degradation of beta and matching characteristics due to reverse
biasing of the base-emitter junction.
The SSM2212 is also an ideal choice for accurate and reliable
current biasing and mirroring circuits. Furthermore, because a
current mirror’s accuracy degrades exponentially with mismatches
of V
BE
between transistor pairs, the low V
OS
of the SSM2212
does not need offset trimming in most circuit applications.
The SSM2212 performance and characteristics are guaranteed
over the extended temperature range of −40°C to +85°C.
Rev.
B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©
2010
Analog Devices, Inc. All rights reserved.
SSM2212
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration............................................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance .......................................................................4
ESD Caution...................................................................................4
Typical Performance Characteristics ..............................................5
Applications Information .................................................................8
Fast Logarithmic Amplifier..........................................................8
Outline Dimensions ..........................................................................9
Ordering Guide .............................................................................9
REVISION HISTORY
7/10—Rev. A to Rev. B
Changes to Figure 1.......................................................................... 1
6/10—Rev. 0 to Rev. A
Changes to Fast Logarithmic Amplifier Section .......................... 8
6/10—Revision 0: Initial Version
Rev. B | Page 2 of 12
SSM2212
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V
CB
= 15 V, I
O
= 10 μA, T
A
= 25°C, unless otherwise specified.
Table 1.
Parameter
DC AND AC CHARACTERISTICS
Current Gain
1
Symbol
h
FE
I
C
= 1 mA
−40°C ≤ T
A
≤ +85°C
I
C
= 10 μA
−40°C ≤ T
A
≤ +85°C
10 μA ≤ I
C
≤ 1 mA
I
C
= 1 mA, V
CB
= 0 V
f
O
= 10 Hz
f
O
= 100 Hz
f
O
= 1 kHz
f
O
= 10 kHz
I
C
= 1 mA
V
CB
= 0 V, I
C
= 1 mA
−40°C ≤ T
A
≤ +85°C
0 V ≤ V
CB
≤ V
MAX 4
,1 μA ≤ I
C
≤ 1 mA
5
1 μA ≤ I
C
≤ 1 mA
5
, V
CB
= 0 V
−40°C ≤ T
A
≤ +85°C
−40°C ≤ T
A
≤ +85°C, V
OS
trimmed to 0 V
I
C
= 100 mA, V
CE
= 10 V
V
CB
= V
MAX
−40°C ≤ T
A
≤ +85°C
V
CC
= V
MAX 6, 7
−40°C ≤ T
A
≤ +85°C
V
CE
= V
MAX
, V
BE
= 0 V
6, 7
−40°C ≤ T
A
≤ +85°C
I
C
= 10 μA
−40°C ≤ T
A
≤ +85°C
I
C
= 10 μA
−40°C ≤ T
A
≤ +85°C
I
C
= 10 μA
6
, −40°C ≤ T
A
≤ +85°C
I
C
= 1 mA, I
B
= 100 μA
V
CB
= 15 V, I
E
= 0 μA
10 μA ≤ I
C
≤ 10 mA
6
V
CC
= 0 V
300
300
200
200
605
550
0.5
1.6
0.9
0.85
0.85
0.4
10
10
5
0.08
0.03
40
200
25
3
35
4
35
4
500
500
500
50
50
6.2
13
150
0.2
1.6
5
2
1
1
1
200
220
50
70
1
0.3
%
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
μV p-p
μV
μV
μV
μV
μV/°C
μV/°C
V
MHz
pA
nA
pA
nA
pA
nA
nA
nA
nA
nA
pA/°C
V
pF
Ω
pF
Text Conditions/Comments
Min
Typ
Max
Unit
Current Gain Match
2
Noise Voltage Density
3
Δh
FE
e
N
Low Frequency Noise (0.1 Hz to 10 Hz)
Offset Voltage
Offset Voltage Change vs. V
CB
Offset Voltage Change vs. I
C
Offset Voltage Drift
Breakdown Voltage
Gain Bandwidth Product
Collector-to-Base Leakage Current
Collector-to-Collector Leakage Current
Collector-to-Emitter Leakage Current
Input Bias Current
Input Offset Current
Input Offset Current Drift
Collector Saturation Voltage
Output Capacitance
Bulk Resistance
Collector-to-Collector Capacitance
1
2
e
N
p-p
V
OS
ΔV
OS
/ΔV
CB
ΔV
OS
/ΔI
C
ΔV
OS
/ΔT
BV
CEO
f
T
I
CBO
I
CC
I
CES
I
B
I
OS
ΔI
OS
/ΔT
V
CE (SAT)
C
OB
R
BE
C
CC
40
0.05
23
0.3
35
Current gain is guaranteed with collector-to-base voltage (V
CB
) swept from 0 V to V
MAX
at the indicated collector currents.
Current gain match (Δh
FE
) is defined as follows: Δh
FE
= (100(ΔI
B
)(h
FE min
)/I
C
).
3
Noise voltage density is guaranteed, but not 100% tested.
4
This is the maximum change in V
OS
as V
CB
is swept from 0 V to 40 V.
5
Measured at I
C
= 10 μA and guaranteed by design over the specified range of I
C
.
6
Guaranteed by design.
7
I
CC
and I
CES
are verified by measurement of I
CBO
.
Rev. B | Page 3 of 12
SSM2212
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Breakdown Voltage of
Collector-to-Base Voltage (BV
CBO
)
Breakdown Voltage of
Collector-to-Emitter Voltage (BV
CEO
)
Breakdown Voltage of
Collector-to-Collector Voltage (BV
CC
)
Breakdown Voltage of
Emitter-to-Emitter Voltage (BV
EE
)
Collector Current (I
C
)
Emitter Current (I
E
)
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
Rating
40 V
40 V
40 V
40 V
20 mA
20 mA
−65°C to +150°C
−40°C to +85°C
−65°C to +150°C
300°C
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
8-Lead SOIC (R-8)
θ
JA
120
θ
JC
45
Unit
°C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. B | Page 4 of 12
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