IS61NLP25618A-200B2 datasheet, PDF

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IS61NLP25618A-200B2: DescriptionZBT SRAM, 256KX18, 3.1ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119; Categorystorage storage; File Size505KB，29 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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IS61NLP25618A-200B2 Overview

ZBT SRAM, 256KX18, 3.1ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119

IS61NLP25618A-200B2 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	BGA
package instruction	BGA, BGA119,7X17,50
Contacts	119
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	3.1 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	200 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	4718592 bit
Memory IC Type	ZBT SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA119,7X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	2.41 mm
Maximum standby current	0.03 A
Minimum standby current	3.14 V
Maximum slew rate	0.2 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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IS61NLP12832B

IS61NLP12836B/IS61NVP12836B

IS61NLP25618A/IS61NVP25618A

128K x 32, 128K x 36, and 256K x 18

4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM

SEPTEMBER 2007

FEATURES

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

• Clock controlled, registered address,

data and control

DESCRIPTION

The 4 Meg 'NLP/NVP' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

networking and communications applications. They are

organized as 128K words by 32 bits, 128K words by 36

bits, and 256K words by 18 bits, fabricated with

ISSI

advanced CMOS technology.

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

All synchronous inputs pass through registers are controlled

by a positive-edge-triggered single clock input. Operations

may be suspended and all synchronous inputs ignored

when Clock Enable,

CKE is HIGH. In this state the internal

device will hold their previous values.

All Read, Write and Deselect cycles are initiated by the ADV

input. When the ADV is HIGH the internal burst counter

is incremented. New external addresses can be loaded

when ADV is LOW.

Write cycles are internally self-timed and are initiated

by the rising edge of the clock inputs and when

LOW. Separate byte enables allow individual bytes to be

written.

A burst mode pin (MODE) defines the order of the burst

sequence. When tied HIGH, the interleaved burst sequence

is selected. When tied LOW, the linear burst sequence is

selected.

• Interleaved or linear burst sequence control us-

ing MODE input

• Three chip enables for simple depth expansion

and address pipelining

• Power Down mode

• Common data inputs and data outputs

•

CKE

pin to enable clock and suspend operation

• JEDEC 100-pin TQFP, 165-ball PBGA and 119-

ball PBGA packages

• Power supply:

NVP: V

2.5V (± 5%), V

ddq

2.5V (± 5%)

NLP: V

3.3V (± 5%), V

ddq

3.3V/2.5V (± 5%)

• Industrial temperature available

• Lead-free available

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

-250

2.6

250

-200

3.1

200

Units

MHz

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com

Rev. D

09/10/07

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