PRELIMINARY
PDM4M4120
1M x 32 CMOS
Static RAM Module
Features
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2
3
4
5
6
7
8
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High-density 4 megabyte Static RAM module
Low profile 72-pin ZIP (Zig-zag In-line vertical
Package) or 72-pin SIMM and Angled SIMM
(Single In-line Memory Module)
Fast access time: 15ns (max.)
Surface mounted plastic components on an epoxy
laminate (FR-4) substrate Single 5V (
±
10%) power
supply
Multiple V
SS
pins and decoupling capacitors for
maximum noise immunity
Inputs/outputs directly TTL compatible
The PDM4M4120 is packaged in a 72-pin FR-4 ZIP
(Zig-zag In-line vertical Package) or a 72-pin SIMM or
Angled SIMM (Single In-line Memory Module). The
ZIP configuration allows 72 pins to be placed on a
package 3.950" long and 0.365" wide. At only 0.590"
high, this low-profile package is ideal for systems
with minimum board spacing. The SIMM configura-
tion allows use of edge mounted sockets to secure the
module.
All inputs and outputs of the PDM4M4120 are TTL
compatible and operate from a single 5V supply. Full
asynchronous circuitry requires no clock or refresh for
operation and provides equal access and cycle times
for ease of use.
Four identification pins (PD0, PD1, PD2, PD3) are pro-
vided for applications in which different density
versions of the module are used. In this way, the tar-
get system can read the respective levels of PD0, PD1,
PD2, PD3 to determine a 1M depth.
Description
The PDM4M4120 is a 1M x 32 static RAM module
constructed on an epoxy laminate (FR-4) substrate
using eight 1M x 4 static RAMs in plastic SOJ pack-
ages. Availability of four chip select lines (one for
each of two RAMs) provides byte access. The
PDM4M4120 is available with access times as fast as
15ns with minimal power consumption.
Functional Block Diagram
CS
1
ADDRESS
20
CS
2
CS
3
CS
4
4
PD3-PD0
9
10
11
WE
OE
8
8
1M x 32
RAM
8
8
I/O31-I/O0
12
8-51
Rev 2.3
PRELIMINARY
PDM4M4120
Pin Configuration
(1)
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
NC
PD2
Vss
PD1
I/O8
I/O9
I/O10
I/O11
A0
A1
A2
I/O12
I/O13
I/O14
I/O15
Vss
A15
CS
2
PD0 - Vss
PD1 - NC
PD2 - Vss
PD3 - NC
Pin Assignment
Pin
Signal
Data Inputs/Outputs
Addresses
Chip Selects
Write Enable
Output Enable
Depth Identification
Power
Ground
I/O31-I/O0
A19-A0
CS
NC
PD3
PD0
I/O0
I/O1
I/O2
I/O3
Vcc
A7
A8
A9
I/O4
I/O5
I/O6
I/O7
WE
A14
CS
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
ZIP, SIMM
TOP VIEW
4-
CS
1
WE
OE
PD3-PD0
V
CC
V
SS
CS
3
A16
Vss
I/O16
I/O17
I/O18
I/O19
A10
A11
A12
A13
I/O20
I/O21
I/O22
I/O23
Vss
A19
NC
NOTE:
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
CS
4
A17
OE
I/O24
I/O25
I/O26
I/O27
A3
A4
A5
Vcc
A6
I/O28
I/O29
I/O30
I/O31
A18
NC
1. Pins 3, 4, 6, and 7 (PD0, PD1, PD02, and PD3
respectively) are read by the user to determine the
density of the module. If PD0 reads V
SS
, PD1 reads
NC, PD2 reads V , PD3 reads NC then the mod-
SS
ule has a 1M depth.
8-52
Rev 2.3
PRELIMINARY
PDM4M4120
Truth Table
Mode
Deselect/
Power-down
Read
Write
Deselect
CS
OE
WE
Output
High-Z
DATA
OUT
DATA
IN
High-Z
Power
Standby
Active
Active
Active
1
2
3
H
L
L
L
X
L
X
H
X
H
L
H
Absolute Maximum Ratings
(1)
Symbol
V
TERM
T
BIAS
T
STG
T
A
P
T
I
OUT
NOTE:
Rating
Terminal Voltage with Respect to V
SS
Temperature Under Bias
Storage Temperature
Operating Temperature
Power Dissipation
DC Output Current
Com’l.
–0.5 to +7.0
–10 to +85
–55 to +125
0 to +70
1.0
50
Ind.
–0.5 to +7.0
–10 to +85
–65 to +150
0 to +70
1.0
50
Unit
V
°
C
°
C
°
C
W
mA
4
5
6
7
8
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Recommended DC Operating Conditions
Symbol
V
CC
V
SS
Commercial
Parameter
Supply Voltage
Supply Voltage
Ambient Temperature
Min.
4.75
0
0
Typ.
5.0
0
25
Max.
5.25
0
70
Unit
V
V
°
C
9
10
11
12
Rev 2.3
8-53
PRELIMINARY
PDM4M4120
DC Electrical Characteristics
(V
CC
= 5.0V
±
5%, T
A
= 0
°
C to 70
°
C)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
I
LI
I
LI
I
LO
V
OL
V
OH
V
IH
V
IL
NOTE
Input Leakage Current
(Address)
Input Leakage Current
(Data)
Output Leakage Current
Output Low Voltage
Output High Voltage
Input High Voltage
Input Low Voltage
V
CC
= Max.,V
IN
= V
SS
to V
CC
V
CC
= Max., V
IN
= V
SS
to V
CC
V
OUT
= V
SS
to V
CC
, V
CC
= Max.,
CS
= V
IH
I
OL
= 8 mA, V = Min.
CC
I
OL
= –4 mA, V = Min.
CC
—
—
—
—
2.4
2.2
–0.5
(1)
80
10
10
0.4
—
6.0
0.8
µ
A
µ
A
µ
A
V
V
V
V
1. V
IL
= –1.5V for pulse widths less than 10 ns, once per cycle.
Power Supply Characteristics
Symbol
Parameter
Max
(1)
Unit
I
CC
I
SB
I
SB1
Operating Current
CS
= V , V
CC
= Max., f = f
IL
MAX
, Outputs Open
CS
1280
480
120
mA
mA
mA
Standby Current
≥
V
IH
, V
CC
= Max., f = f
MAX
, Outputs Open
Full Standby Current
CS
≥
V
CC
– 0.2V,
f = 0, V
IN
> V
CC
– 0.2V or < 0.2V, Outputs Open
NOTE
1. Preliminary specification only.
Capacitance
(1)
(T
A
= +25
°
C, f = 1.0 MHz)
Symbol
Parameter
Max.
Unit
C
I/O
C
IN(1)
C
IN(2)
C
IN(3)
NOTE
Data I/O Capacitance, V
IN
= 0V
Input Capacitance, (Address) V
IN
= 0V
Input Capacitance, (
WE
,
OE
) V
IN
= 0V
Input Capacitance, (
CS
), V
IN
= 0V
15
60
75
20
pF
pF
pF
pF
1. This parameter is determined by device characteristics but is not production tested.
8-54
Rev 2.3
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