K3N3C3000D-D(G)C
4M-Bit (512Kx8) CMOS MASK ROM
FEATURES
•
524,288x8 bit organization
•
Access time : 80ns(Max.)
•
Supply voltage : single +5V
•
Current consumption
Operating : 50mA(Max.)
Standby : 50µA(Max.)
•
Fully static operation
•
All inputs and outputs TTL compatible
•
Three state outputs
•
Package
-. K3N3C3000D-DC : 32-DIP-600
-. K3N3C3000D-GC : 32-SOP-525
CMOS MASK ROM
GENERAL DESCRIPTION
The K3N3C3000D-D(G)C is a fully static mask programmable
ROM organized 524,288 x 8 bit. It is fabricated using silicon
gate CMOS process technology.
This device operates with a 5V single power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The K3N3C3000D-DC is packaged in a 32-DIP and the
K3N3C3000D-GC in a 32-SOP.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
A
18
.
.
.
.
.
.
.
.
A
0
X
BUFFERS
AND
DECODER
MEMORY CELL
MATRIX
(524,288x8)
N.C
A
16
A
15
A
12
1
2
3
4
5
6
7
8
9
32 V
CC
31 A
18
30 A
17
29 A
14
28 A
13
27 A
8
Y
BUFFERS
AND
DECODER
SENSE AMP.
BUFFERS
A
7
A
6
A
5
A
4
A
3
DIP
&
SOP
26 A
9
25 A
11
24 OE
23 A
10
21 CE
21 Q
7
20 Q
6
19 Q
5
18 Q
4
17 Q
3
. . .
A
1
A
2
10
11
12
13
14
15
CE
OE
CONTROL
LOGIC
Q
0
Q
7
A
0
Q
0
Q
1
Q
2
Pin Name
A
0
- A
18
Q
0
- Q
7
CE
OE
V
CC
V
SS
N.C
Pin Function
Address Inputs
Data Outputs
Chip Enable
Output Enable
Power(+5V)
Ground
No Connection
V
SS
16
K3N3C3000D-D(G)C
K3N3C3000D-D(G)C
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on Any Pin Relative to V
SS
Temperature Under Bias
Storage Temperature
Symbol
V
IN
T
BIAS
T
STG
Rating
CMOS MASK ROM
Unit
V
°C
°C
-0.3 to +7.0
-10 to +85
-55 to +150
NOTE
: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to V
SS
, T
A
=0 to 70°C)
Item
Supply Voltage
Supply Voltage
Symbol
V
CC
V
SS
Min
4.5
0
Typ
5.0
0
Max
5.5
0
Unit
V
V
DC CHARACTERISTICS
Parameter
Operating Current
Standby Current(TTL)
Standby Current(CMOS)
Input Leakage Current
Output Leakage Current
Input High Voltage, All Inputs
Input Low Voltage, All Inputs
Output High Voltage Level
Output Low Voltage Level
Symbol
I
CC
I
SB1
I
SB2
I
LI
I
LO
V
IH
V
IL
V
OH
V
OL
I
OH
=-400µA
I
OL
=2.1mA
Test Conditions
Cycle=5MHz, all outputs open
CE=OE=V
IL
, V
IN
=0.6V to 2.4V (AC Test Condition)
CE=V
IH
, all outputs open
CE=V
CC
, all outputs open
V
IN
=0 to V
CC
V
OUT
=0 to V
CC
Min
-
-
-
-
-
2.2
-0.3
2.4
-
Max
50
1
50
10
10
V
CC
+0.3
0.8
-
0.4
Unit
mA
mA
µA
µA
µA
V
V
V
V
NOTE
: Minimum DC Voltage(V
IL
) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage(V
IH
) is V
CC
+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
CE
H
L
OE
X
H
L
Mode
Standby
Operating
Operating
Data
High-Z
High-Z
Dout
Power
Standby
Active
Active
CAPACITANCE
(T
A
=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
C
OUT
C
IN
Test Conditions
V
OUT
=0V
V
IN
=0V
Min
-
-
Max
10
10
Unit
pF
pF
NOTE
: Capacitance is periodically sampled and not 100% tested.
K3N3C3000D-D(G)C
TEST CONDITIONS
Item
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Levels
Output Loads
Value
CMOS MASK ROM
AC CHARACTERISTICS
(T
A
=0°C to +70°C, V
CC
=5V±10%, unless otherwise noted.)
0.6V to 2.4V
10ns
0.8V and 2.0V
1 TTL Gate and C
L
=100pF
READ CYCLE
Item
Read Cycle Time
Chip Enable Access Time
Address Access Time
Output Enable Access Time
Output or Chip Disable to
Output High-Z
Output Hold from Address Change
Symbol
t
RC
t
ACE
t
AA
t
OE
t
DF
t
OH
0
K3N3C3D-D(G)C08
Min
80
80
80
40
20
0
Max
K3N3C3D-D(G)C10
Min
100
100
100
50
20
0
Max
K3N3C3D-D(G)C12
Min
120
120
120
60
20
Max
Unit
ns
ns
ns
ns
ns
ns
TIMING DIAGRAM
READ
ADD
ADD1
t
RC
t
ACE
ADD2
t
DF(Note)
CE
t
OE
OE
t
OH
D
OUT
VALID DATA
VALID DATA
t
AA
NOTE :
t
DF
is defined as the time at which the outputs achieve the open circuit condition and is not referenced to V
OH
or
V
OL
level.
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