MSM5412222A-30TS-K datasheet, PDF

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MSM5412222A-30TS-K: DescriptionMemory Circuit, 256KX12, CMOS, PDSO44, 0.400 INCH, 0.8 MM PITCH, PLASTIC, TSOP2-44; Categorystorage storage; File Size69KB，13 Pages; ManufacturerOKI; Websitehttp://www.oki.com

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MSM5412222A-30TS-K Overview

Memory Circuit, 256KX12, CMOS, PDSO44, 0.400 INCH, 0.8 MM PITCH, PLASTIC, TSOP2-44

MSM5412222A-30TS-K Parametric

Parameter Name	Attribute value
Maker	OKI
Parts packaging code	TSOP2
package instruction	TSOP2,
Contacts	44
Reach Compliance Code	unknown
JESD-30 code	R-PDSO-G44
length	18.41 mm
memory density	3145728 bit
Memory IC Type	MEMORY CIRCUIT
memory width	12
Number of functions	1
Number of terminals	44
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX12
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
width	10.16 mm

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OKI

Semiconductor

MSM5412222A

262,214-Word x 12-Bit Field Memory

DESCRIPTION

REVISION-3 1999.6.10

The OKI MSM5412222A is a high performance 3-Mbit, 256K X 12-bit, Field Memory. It is

especially designed for high-speed serial access applications such as HDTVs, conventional

NTSC TVs, VTRs, digital movies and Multi-media systems. MSM5412222A is a FRAM for wide

or low end use in general commodity TVs and VTRs exclusively. MSM5412222A is not

designed for high end use in medical systems, professional graphics systems which require

long term picture storage, data storage systems and others. Two or more MSM5412222As can

be cascaded directly without any delay devices between them. (Cascading provides larger

storage depth or a longer delay).

Each of the 12-bit planes has separate serial write and read ports. These employ independent

control clocks to support asynchronous read and write operations. Different clock rates are also

supported, which allow alternate data rates between write and read data streams.

The MSM5412222A provides high speed FIFO, First-In First-Out, operation without external

refreshing: MSM5412222A refreshes its DRAM storage cells automatically, so that it appears

fully static to the users.

Moreover, fully static type memory cells and decoders for serial access enable the refresh free

serial access operation, so that serial read and/or write control clock can be halted high or low

for any duration as long as the power is on. Internal conflicts of memory access and refreshing

operations are prevented by special arbitration logic.

The MSM5412222A’s function is simple, and similar to a digital delay device whose delay-bit-

length is easily set by reset timing. The delay length, and the number of read delay clocks

between write and read, is determined by externally controlled write and read reset timings.

Additional SRAM serial registers, or line buffers for the initial access of 256 X 12-bit enable high

speed first-bit-access with no clock delay just after the write or read reset timings.

Additionally, the MSM5412222A has a write mask function or input enable function (IE), and

read-data skipping function or output enable function (OE). The differences between write

enable (WE) and input enable (IE), and between read enable (RE) and output enable (OE) are

that WE and RE can stop serial write/read address increments, but IE and OE cannot stop the

increment, when write/read clocking is continuously applied to MSM5412222A. The input

enable (IE) function allows the user to write into selected locations of the memory only, leaving

the rest of the memory contents unchanged. This facilitates data processing to display a

“picture in picture” on a TV screen.

The MSM5412222A is similar in operation and functionality to OKI 1-Mbit Field Memory

MSM514222C and 2-Mbit Field Memory MSM518222A. Three MSM514222Cs or one

MSM514222C plus one MSM518222A can be replaced simply by one MSM5412222A.

OKI

Semiconductor

MSM5412222A

OPERATION

Write Operation

The write operation is controlled by three clocks, SWCK, RSTW, and WE. Write operation is

accomplished by cycling SWCK, and holding WE high after the write address pointer reset

operation or RSTW.

Each write operation, which begins after RSTW, must contain at least 80 active write cycles,

i.e. SWCK cycles while WE is high. To transfer the last data to the DRAM array, which at that

time is stored in the serial data registers attached to the DRAM array, an RSTW operation is

required after the last SWCK cycle.

Note that every write timing of MSM5412222A is delayed by one clock compared with read

timings for easy cascading without any interface delay devices.

Write Reset : RSTW

The first positive transition of SWCK after RSTW becomes high resets the write address

counters to zero. RSTW setup and hold times are referenced to the rising edge of SWCK.

Because the write reset function is solely controlled by the SWCK rising edge after the high

level of RSTW, the states of WE and IE are ignored in the write reset cycle.

Before RSTW may be brought high again for a further reset operation, it must be low for at

least two SWCK cycles.

Data Inputs : D

0 - 11

Write Clock : SWCK

The SWCK latches the input data on chip when WE is high, and also increments the internal

write address pointer. Data-in setup time t

, and hold time t

are referenced to the rising

edge of SWCK.

Write Enable : WE

WE is used for data write enable/disable control. WE high level enables the input, and WE

low level disables the input and holds the internal write address pointer. There are no WE

disable time (low) and WE enable time (high) restrictions, because the MSM5412222A is in

fully static operation as long as the power is on. Note that WE setup and hold times are

referenced to the rising edge of SWCK.

Input Enable : IE

IE is used to enable/disable writing into memory. IE high level enables writing. The internal

write address pointer is always incremented by cycling SWCK regardless of the IE level.

Note that IE setup and hold times are referenced to the rising edge of SWCK.

MSM5412222A-30TS-K Related Products

	MSM5412222A-30TS-K	MSM5412222A-25TS-K	MSM5412222A-30JS	MSM5412222A-25JS
Description	Memory Circuit, 256KX12, CMOS, PDSO44, 0.400 INCH, 0.8 MM PITCH, PLASTIC, TSOP2-44	Memory Circuit, 256KX12, CMOS, PDSO44, 0.400 INCH, 0.8 MM PITCH, PLASTIC, TSOP2-44	Memory Circuit, 256KX12, CMOS, PDSO40, 0.400 INCH, 1.27 MM PITCH, PLASTIC, SOJ-40	Memory Circuit, 256KX12, CMOS, PDSO40, 0.400 INCH, 1.27 MM PITCH, PLASTIC, SOJ-40
Maker	OKI	OKI	OKI	OKI
Parts packaging code	TSOP2	TSOP2	SOJ	SOJ
package instruction	TSOP2,	TSOP2,	SOJ,	SOJ,
Contacts	44	44	40	40
Reach Compliance Code	unknown	unknown	unknown	unknown
JESD-30 code	R-PDSO-G44	R-PDSO-G44	R-PDSO-J40	R-PDSO-J40
length	18.41 mm	18.41 mm	26.03 mm	26.03 mm
memory density	3145728 bit	3145728 bit	3145728 bit	3145728 bit
Memory IC Type	MEMORY CIRCUIT	MEMORY CIRCUIT	MEMORY CIRCUIT	MEMORY CIRCUIT
memory width	12	12	12	12
Number of functions	1	1	1	1
Number of terminals	44	44	40	40
word count	262144 words	262144 words	262144 words	262144 words
character code	256000	256000	256000	256000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C
organize	256KX12	256KX12	256KX12	256KX12
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP2	TSOP2	SOJ	SOJ
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE	SMALL OUTLINE
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	3.75 mm	3.75 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING	J BEND	J BEND
Terminal pitch	0.8 mm	0.8 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
width	10.16 mm	10.16 mm	10.16 mm	10.16 mm

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