MPC8241TZQ166D datasheet, PDF - EEWORLD Datasheet

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MPC8241TZQ166D: DescriptionRISC Microprocessor, 32-Bit, 166MHz, CMOS, PBGA357,; CategoryThe embedded processor and controller Microcontrollers and processors; File Size876KB，64 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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MPC8241TZQ166D Overview

RISC Microprocessor, 32-Bit, 166MHz, CMOS, PBGA357,

MPC8241TZQ166D Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Motorola ( NXP )
package instruction	BGA, BGA357,19X19,50
Reach Compliance Code	unknown
bit size	32
JESD-30 code	S-PBGA-B357
Number of terminals	357
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA357,19X19,50
Package shape	SQUARE
Package form	GRID ARRAY
power supply	1.8,3.3 V
Certification status	Not Qualified
speed	166 MHz
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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Advance Information

MPC8241EC

Rev. 6.1, 2/2004

MPC8241

Integrated Processor

Hardware Specifications

The MPC8241 combines a MPC603e PowerPC™ core microprocessor with a PCI bridge. The

PCI support on the MPC8241 allows system designers to use peripherals that are already

designed for the PCI and other standard interfaces to design systems rapidly. The MPC8241

also integrates a high-performance memory controller that supports various types of ROM and

SDRAM. The MPC8241 is the second of a family of products that provides system-level

support for industry standard interfaces with a MPC603e processor core.

This document describes pertinent electrical and physical characteristics of the MPC8241,

which is based on the MPC8245 design. For information about functional characteristics of

the processor, refer to the

MPC8245 Integrated Processor User’s Manual

(MPC8245UM).

This document contains the following topics:

Topic

Section 1, “Overview”

Section 2, “Features”

Section 3, “General Parameters”

Section 4, “Electrical and Thermal Characteristics”

Section 5, “Package Description”

Section 6, “PLL Configuration”

Section 7, “System Design Information”

Section 8, “Document Revision History”

Section 9, “Ordering Information”

Page

To locate any published errata or updates for this document, refer to the web site at

http://www.motorola.com/semiconductors.

Overview

The MPC8241 integrated processor is comprised of a peripheral logic block and a 32-bit

superscalar MPC603e core, as shown in Figure 1.

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Features

The peripheral logic integrates a PCI bridge, dual universal asynchronous receiver/transmitter (DUART),

memory controller, DMA controller, PIC interrupt controller, a message unit (and I

O interface), and an I

controller. The processor core is a full-featured, high-performance processor with floating-point support,

memory management, 16-Kbyte instruction cache, 16-Kbyte data cache, and power management features.

The integration reduces the overall packaging requirements and the number of discrete devices required for

an embedded system.

The MPC8241 contains an internal peripheral logic bus that interfaces the processor core to the peripheral

logic. The core can operate at a variety of frequencies, allowing the designer to trade performance for power

consumption. The processor core is clocked from a separate PLL that is referenced to the peripheral logic

PLL, allowing the microprocessor and the peripheral logic block to operate at different frequencies while

maintaining a synchronous bus interface. The interface uses a 64- or 32-bit data bus (depending on memory

data bus width) and a 32-bit address bus along with control signals that enable the interface between the

processor and peripheral logic to be optimized for performance. PCI accesses to the MPC8241 memory

space are passed to the processor bus for snooping when snoop mode is enabled.

The processor core and peripheral logic serve the general purposes of a variety of embedded applications.

The MPC8241 can be used as either a PCI host or PCI agent controller.

•

Features

Processor core

— High-performance, superscalar processor core

— Integer unit (IU), floating-point unit (FPU) (software enabled or disabled), load/store unit

(LSU), system register unit (SRU), and a branch processing unit (BPU)

— 16-Kbyte instruction cache

— 16-Kbyte data cache

— Lockable L1 caches—entire cache or on a per-way basis up to three of four ways

— Dynamic power management—supports 60x nap, doze, and sleep modes

Peripheral logic

— Peripheral logic bus

– Supports various operating frequencies and bus divider ratios

– 32-bit address bus, 64-bit data bus

– Supports full memory coherency

– Decoupled address and data buses for pipelining of peripheral logic bus accesses

– Store gathering on peripheral logic bus-to-PCI writes

— Memory interface

– Supports up to 2 Gbytes of SDRAM memory

– High-bandwidth data bus (32- or 64-bit) to SDRAM

– Programmable timing supporting SDRAM

– Supports 1 to 8 banks of 16-, 64-, 128-, 256-, or 512-Mbit memory devices

– Write buffering for PCI and processor accesses

– Supports normal parity, read-modify-write (RMW), or ECC

– Data-path buffering between memory interface and processor

Major features of the MPC8241 are as follows:

•

MOTOROLA

MPC8241 Integrated Processor Hardware Specifications

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

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