CD4011AD3 datasheet, PDF - EEWORLD Datasheet

CD4011AD3: DescriptionIC,LOGIC GATE,QUAD 2-INPUT NAND,CMOS,DIP,14PIN,CERAMIC; Categorylogic logic; File Size640KB，7 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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CD4011AD3 Overview

IC,LOGIC GATE,QUAD 2-INPUT NAND,CMOS,DIP,14PIN,CERAMIC

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Renesas Electronics Corporation
package instruction	DIP, DIP14,.3
Reach Compliance Code	not_compliant
JESD-30 code	R-XDIP-T14
JESD-609 code	e0
Load capacitance (CL)	15 pF
Logic integrated circuit type	NAND GATE
MaximumI(ol)	0.00031 A
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	5/15 V
Prop。Delay @ Nom-Sup	75 ns
Certification status	Not Qualified
Schmitt trigger	NO
Filter level	38535Q/M;38534H;883B
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL

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