INTEGRATED CIRCUITS
GTL2000
22-bit bi-directional low voltage translator
Product data
Supersedes data of 2000 Jan 25
2003 Apr 01
Philips
Semiconductors
Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
GTL2000
FEATURES
DESCRIPTION
The Gunning Transceiver Logic — Transceiver Voltage Clamps
(GTL-TVC) provide high-speed voltage translation with low
ON-state resistance and minimal propagation delay. The GTL2000
provides 22 NMOS pass transistors (Sn and Dn) with a common
gate (G
REF
) and a reference transistor (S
REF
and D
REF
). The device
allows bi-directional voltage translations between 1.0 V and 5.0 V
without use of a direction pin.
When the Sn or Dn port is low the clamp is in the ON-state and a
low resistance connection exists between the Sn and Dn ports.
Assuming the higher voltage is on the Dn port, when the Dn port is
high, the voltage on the Sn port is limited to the voltage set by the
reference transistor (S
REF
). When the Sn port is high, the Dn port is
pulled to V
CC
by the pull up resistors. This functionality allows a
seamless translation between higher and lower voltages selected by
the user, without the need for directional control.
All transistors have the same electrical characteristics and there is
minimal deviation from one output to another in voltage or
propagation delay. This is a benefit over discrete transistor voltage
translation solutions, since the fabrication of the transistors is
symmetrical. Because all transistors in the device are identical,
S
REF
and D
REF
can be located on any of the other twenty-two
matched Sn/Dn transistors, allowing for easier board layout. The
translator’s transistors provides excellent ESD protection to lower
voltage devices and at the same time protect less ESD resistant
devices.
•
22-bit bi-directional low voltage translator
•
Allows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V,
2.5 V, 3.3 V, and 5 V busses which allows direct interface with
GTL, GTL+, LVTTL/TTL and 5 V CMOS levels
•
Provides bi-directional voltage translation with no direction pin
•
Low 6.5
Ω
RDS
ON
resistance between input and output pins
(Sn/Dn)
•
Supports hot insertion
•
No power supply required - Will not latch up
•
5 V tolerant inputs
•
Low stand-by current
•
Flow-through pinout for ease of printed circuit board trace routing
•
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V
MM per JESD22-A115, and 1000 V per JESD22-C101
•
Package offer: SSOP48, TSSOP48
APPLICATIONS
•
Any application that requires bi-directional or unidirectional
voltage level translation from any voltage between 1.0 V & 5.0 V
to any voltage between 1.0 V & 5.0 V
•
The open drain construction with no direction pin is ideal for
bi-directional low voltage (e.g., 1.0 V, 1.2 V, 1.5 V, or 1.8 V)
processor I
2
C port translation to the normal 3.3 V and/or 5.0 V I
2
C
bus signal levels or GTL/GTL+ translation to LVTTL/TTL signal
levels.
ORDERING INFORMATION
PACKAGES
48-Pin Plastic SSOP
TEMPERATURE RANGE
-40 to +85
°C
ORDER CODE
GTL2000DL
TOPSIDE MARK
GTL2000DL
DWG NUMBER
SOT370-1
SOT362-1
48-Pin Plastic TSSOP
-40 to +85
°C
GTL2000DGG
GTL2000DGG
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
2003 Apr 01
2
Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
GTL2000
PIN CONFIGURATION
GND 1
S
REF
2
S
1
3
S
2
4
S
3
5
S
4
6
S
5
7
S
6
8
S
7
9
S
8
10
S
9
11
S
10
12
S
11
13
S
12
14
S
13
15
S
14
16
S
15
17
S
16
18
S
17
19
S
18
20
S
19
21
S
20
22
S
21
23
S
22
24
G
REF
D
REF
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
11
D
12
D
13
D
14
D
15
D
16
D
17
D
18
D
19
D
20
D
21
D
22
SA00521
FUNCTION TABLE
HIGH to LOW translation assuming Dn is at the higher voltage level
GREF
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DREF
H
H
H
L
SREF
0V
V
TT
V
TT
0 - V
TT
In-Dn
X
H
L
X
Out-Sn
X
V
TT1
L
2
X
Transistor
Off
On
On
Off
H
H
H
L
H = High voltage level
L = Low voltage level
X = Don’t Care
NOTES:
1. Sn is not pulled up or pulled down.
2. Sn follows the Dn input low.
3. G
REF
should be at least 1.5 V higher than S
REF
for best
translator operation.
4. V
TT
is equal to the S
REF
voltage.
FUNCTION TABLE
LOW to HIGH translation assuming Dn is at the higher voltage level
GREF
H
H
H
L
DREF
H
H
H
L
SREF
0V
V
TT
V
TT
In-Sn
X
V
TT
L
X
Out-Dn
X
H
1
L
2
X
Transistor
Off
nearly off
On
Off
0 - V
TT
H = High voltage level
L = Low voltage level
X = Don’t Care
NOTES:
1. Dn is pulled up to V
CC
through an external resistor.
2. Dn follows the Sn input low.
3. G
REF
should be at least 1.5 V higher than S
REF
for best
translator operation.
4. V
TT
is equal to the S
REF
voltage.
CLAMP SCHEMATIC
D
REF
G
REF
D
1
D
22
PIN DESCRIPTION
PIN
NUMBER
1
2
3 - 24
25 - 46
47
48
SYMBOL
GND
S
REF
S
n
D
n
D
REF
G
REF
NAME AND FUNCTION
Ground (0 V)
Source of reference transistor
Port S
1
to Port S
22
Port D
1
to Port D
22
Drain of reference transistor
Gate of reference transistor
S
REF
S
1
S
22
SA00522
2003 Apr 01
3
Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
GTL2000
APPLICATIONS
Bi-directional translation
For the bi-directional clamping configuration, higher voltage to lower voltage or lower voltage to higher voltage, the G
REF
input must be
connected to D
REF
and both pins pulled to high side V
CC
through a pull-up resistor (typically 200 kΩ). A filter capacitor on D
REF
is
recommended. The processor output can be totem pole or open drain (pull up resistors may be required) and the chipset output can be totem
pole or open drain (pull up resistors are required to pull the Dn outputs to V
CC
). However, if either output is totem pole, data must be
uni-directional or the outputs must be 3-statable and the outputs must be controlled by some direction control mechanism to prevent high to low
contentions in either direction. If both outputs are open drain, no direction control is needed. The opposite side of the reference transistor (S
REF
)
is connected to the processor core power supply voltage. When D
REF
is connected through a 200 kΩ resistor to a 3.3 V to 5.5 V V
CC
supply
and S
REF
is set between1.0 V to V
CC
- 1.5 V, the output of each Sn has a maximum output voltage equal to S
REF
and the output of each Dn
has a maximum output voltage equal to V
CC
.
TYPICAL BI-DIRECTIONAL VOLTAGE TRANSLATION
1.8 V
1.5 V
1.2 V
1.0 V
GND
V
CORE
S
REF
S1
G
REF
D
REF
D1
D2
V
CC
5V
GTL2002
200 KΩ
TOTEM POLE OR
OPEN DRAIN I/O
CPU I/O
S2
CHIPSET I/O
3.3 V
INCREASE BIT
SIZE BY USING
10 BIT GTL2010 OR
22 BIT GTL2000
V
CC
S3
S4
S5
Sn
D3
D4
D5
Dn
SA00642
CHIPSET I/O
Figure 1. Bi-directional translation to multiple higher voltage levels such as an I
2
C bus application
2003 Apr 01
4
Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
GTL2000
Uni-directional down translation
For uni-directional clamping, higher voltage to lower voltage, the G
REF
input must be connected to D
REF
and both pins pulled to the higher side
V
CC
through a pull-up resistor (typically 200 kΩ). A filter capacitor on D
REF
is recommended. Pull up resistors are required if the chipset I/O are
open drain. The opposite side of the reference transistor (S
REF
) is connected to the processor core supply voltage. When D
REF
is connected
through a 200 kΩ resistor to a 3.3 V to 5.5 V V
CC
supply and S
REF
is set between 1.0 V to V
CC
- 1.5 V, the output of each Sn has a maximum
output voltage equal to S
REF
.
TYPICAL UNI-DIRECTIONAL - HIGH TO LOW VOLTAGE TRANSLATION
1.8 V
1.5 V
1.2 V
1.0 V
GND
EASY MIGRATION TO
LOWER VOLTAGE AS
PROCESSOR GEOMETRY
SHRINKS.
V
CORE
S
REF
S1
G
REF
D
REF
D1
D2
V
CC
5V
GTL2002
200 KΩ
CPU I/O
S2
CHIPSET I/O
TOTEM POLE I/O
SA00643
Figure 2. Uni-directional down translation, to protect low voltage processor pins
Uni-directional up translation
For uni-directional up translation, lower voltage to higher voltage, the reference transistor is connected the same as for a down translation. A
pull-up resistor is required on the higher voltage side (Dn or Sn) to get the full high level, since the GTL-TVC device will only pass the reference
source (S
REF
) voltage as a high when doing an up translation. The driver on the lower voltage side only needs pull-up resistors if it is open
drain.
TYPICAL UNI-DIRECTIONAL - LOW TO HIGH VOLTAGE TRANSLATION
1.8 V
1.5 V
1.2 V
1.0 V
GND
EASY MIGRATION TO
LOWER VOLTAGE AS
PROCESSOR GEOMETRY
SHRINKS.
V
CORE
S
REF
S1
G
REF
D
REF
D1
D2
V
CC
5V
GTL2002
200 KΩ
CPU I/O
TOTEM POLE I/O
OR OPEN DRAIN
S2
CHIPSET I/O
SA00644
Figure 3. Uni-directional up translation, to higher voltage chip sets
2003 Apr 01
5
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