MC68030CRC33C datasheet, PDF - EEWORLD Datasheet

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MC68030CRC33C: Description32-BIT, 33MHz, MICROPROCESSOR, CPGA128, PGA-128; CategoryThe embedded processor and controller Microcontrollers and processors; File Size332KB，48 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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MC68030CRC33C Overview

32-BIT, 33MHz, MICROPROCESSOR, CPGA128, PGA-128

MC68030CRC33C Parametric

Parameter Name	Attribute value
Maker	Motorola ( NXP )
Parts packaging code	PGA
package instruction	PGA,
Contacts	128
Reach Compliance Code	unknown
ECCN code	3A991.A.2
Address bus width	32
bit size	32
boundary scan	NO
maximum clock frequency	33 MHz
External data bus width	32
Format	FIXED POINT
Integrated cache	YES
JESD-30 code	S-CPGA-P128
length	34.545 mm
low power mode	YES
Number of terminals	128
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
speed	33 MHz
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	HCMOS
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
width	34.545 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

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by MC68EC030/D

SEMICONDUCTOR

TECHNICAL DATA

MC68EC030

Technical Summary

Second-Generation 32-Bit Enhanced Embedded

Controller

The MC68EC030 is a 32-bit embedded controller that streamlines the functionality of an MC68030 for

the requirements of embedded control applications. The MC68EC030 is optimized to maintain

performance while using cost-effective memory subsystems. The rich instruction set and addressing

mode capabilities of the MC68020, MC68030, and MC68040 have been maintained, allowing a clear

migration path for M68000 systems. The main features of the MC68EC030 are as follows:

•

Object-Code Compatible with the MC68020, MC68030, and Earlier M68000 Microprocessors

Burst-Mode Bus Interface for Efficient DRAM Access

On-Chip Data Cache (256 Bytes) and On-Chip Instruction Cache (256 Byte)

Dynamic Bus Sizing for Direct Interface to 8-, 16-, and 32-Bit Devices

25- and 40-MHz Operating Frequency (up to 9.2 MIPS)

Advanced Plastic Pin Grid Array Packaging for Through-Hole Applications

Additional features of the MC68EC030 include:

•

Complete 32-Bit Nonmultiplexed Address and Data Buses

Sixteen 32-Bit General-Purpose Data and Address Registers

Two 32-Bit Supervisor Stack Pointers and Eight Special-Purpose Control Registers

Two Access Control Registers Allow Blocks To Be Defined for Cacheability Protection

Pipelined Architecture with Increased Parallelism Allows:

– Internal Caches Accesses in Parallel with Bus Transfers

– Overlapped Instruction Execution

Enhanced Bus Controller Supports Asynchronous Bus Cycles (three clocks minimum),

Synchronous Bus Cycle (two clocks minimum), and Burst Data Transfers (one clock)

Complete Support for Coprocessors with the M68000 Coprocessor Interface

Internal Status Indication for Hardware Emulation Support

4-Gbyte Direct Addressing Range

Implemented in Motorola's HCMOS Technology That Allows CMOS and HMOS (High-Density

NMOS) Gates To Be Combined for Maximum Speed, Low Power, and Small Die Size

•

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

©MOTOROLA INC., 1991

µ MOTOROLA

Rev. 1

INTRODUCTION

The MC68EC030 is an integrated controller that incorporates the capabilities of the MC68030 integer

unit, a data cache, an instruction cache, an access control unit (ACU), and an improved bus controller on

one VLSI device. It maintains the 32-bit registers available with the entire M68000 Family as well as the

32-bit address and data paths, rich instruction set, versatile addressing modes, and flexible coprocessor

interface provided with the MC68020 and MC68030. In addition, the internal operations of this integrated

controller are designed to operate in parallel, allowing instruction execution to proceed in parallel with

accesses to the internal caches and the bus controller.

The MC68EC030 fully supports the nonmultiplexed asynchronous bus of the MC68020 and MC68030

as well as the dynamic bus sizing mechanism that allows the controller to transfer operands to or from

external devices while automatically determining device port size on a cycle-by-cycle basis. In addition to

the asynchronous bus, the MC68EC030 also supports the fast synchronous bus of the MC68030 for off-

chip caches and fast memories. Like the MC68030, the MC68EC030 bus is capable of fetching up to four

long words of data in a burst mode compatible with DRAM chips that have burst capability. Burst mode can

reduce (up to 50 percent) the time necessary to fetch the four long words. The four long words are used

to prefill the on-chip instruction and data caches so that the hit ratio of the caches is improved and the

average access time for operand fetches is minimized.

The MC68EC030 is specifically designed to sustain high performance while using low-cost (DRAM)

memory subsystems. Coupled with the MC88916 clock generation and distribution circuit, the

MC68EC030 provides simple interface to lower speed memory subsystems. The MC88916 (see Figure

1) provides the precise clock signals required to efficiently control memory subsystems, eliminating

system design constraints due to clock generation and distribution.

CONTROLLER

CLOCK (40 MHz)

20 MHz

OSC.

MC88916

MC68EC030

(40 MHz)

BUS CLOCK

(20 MHz)

BUS CLOCK

(40 MHz)

BUS CLOCK

(80 MHz)

Figure 1.

MC68EC030 Clock Circuitry

The block diagram shown in Figure 2 depicts the major sections of the MC68EC030 and illustrates the

autonomous nature of these blocks. The bus controller consists of the address and data pads, the

multiplexers required to support dynamic bus sizing, and a microbus controller that schedules the bus

cycles on the basis of priority. The micromachine contains the execution unit and all related control logic.

Microcode control is provided by a modified two-level store of microROM and nanoROM contained in the

micromachine. Programmed logic arrays (PLAs) are used to provide instruction decode and sequencing

MC68EC030 TECHNICAL DATA

MOTOROLA

MC68030CRC33C Related Products

	MC68030CRC33C	MC68EC030RP40C	MC68EC030CFE25C	MC68EC030FE25C	MC68EC030FE25CB1	MC68030CRC25C	MC68EC030RP25C	MC68EC030RC40C	MC68EC030RC25C
Description	32-BIT, 33MHz, MICROPROCESSOR, CPGA128, PGA-128	Microprocessor, 32-Bit, HCMOS, PPGA117, PLASTIC, PGA-117	32-BIT, 25MHz, MICROPROCESSOR, CQCC132, CERQUAD-132	32-BIT, 25MHz, MICROPROCESSOR, CQCC132, CERQUAD-132	32-BIT, 25MHz, MICROPROCESSOR, CQFP132, CERAMIC, QFP-132	32-BIT, 25 MHz, MICROPROCESSOR, CPGA128, PGA-128	Microprocessor, 32-Bit, HCMOS, PPGA117, PLASTIC, PGA-117	32-BIT, MICROPROCESSOR, PPGA124, PLASTIC, PGA-124	Microprocessor, 32-Bit, HCMOS, PPGA124, PLASTIC, PGA-124
package instruction	PGA,	PGA,	QCCJ,	QCCJ,	QFP,	PGA,	PGA,	PGA,	PGA,
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknow
Address bus width	32	32	32	32	32	32	32	32	32
bit size	32	32	32	32	32	32	32	32	32
boundary scan	NO	NO	NO	NO	NO	NO	NO	NO	NO
External data bus width	32	32	32	32	32	32	32	32	32
Format	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT
Integrated cache	YES	YES	YES	YES	YES	YES	YES	YES	YES
JESD-30 code	S-CPGA-P128	S-PPGA-P117	X-CQCC-J132	X-CQCC-J132	S-CQFP-G132	S-CPGA-P128	S-PPGA-P117	S-PPGA-P124	S-PPGA-P124
low power mode	YES	YES	YES	YES	YES	YES	YES	YES	YES
Number of terminals	128	117	132	132	132	128	117	124	124
Package body material	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	PGA	PGA	QCCJ	QCCJ	QFP	PGA	PGA	PGA	PGA
Package shape	SQUARE	SQUARE	UNSPECIFIED	UNSPECIFIED	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	CHIP CARRIER	CHIP CARRIER	FLATPACK	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum supply voltage	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V
Minimum supply voltage	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	NO	YES	YES	YES	NO	NO	NO	NO
technology	HCMOS	HCMOS	HCMOS	HCMOS	HCMOS	HCMOS	HCMOS	HCMOS	HCMOS
Terminal form	PIN/PEG	PIN/PEG	J BEND	J BEND	GULL WING	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG
Terminal location	PERPENDICULAR	PERPENDICULAR	QUAD	QUAD	QUAD	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR
Maker	Motorola ( NXP )	-	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )
Parts packaging code	PGA	-	QFN	QFN	QFP	PGA	-	PGA	-
Contacts	128	-	132	132	132	128	-	124	-
maximum clock frequency	33 MHz	40 MHz	-	-	25 MHz	25 MHz	25 MHz	40 MHz	25 MHz
length	34.545 mm	-	-	-	24.13 mm	34.545 mm	-	34.545 mm	34.545 mm
speed	33 MHz	-	25 MHz	25 MHz	25 MHz	25 MHz	-	-	-
Terminal pitch	2.54 mm	-	-	-	0.635 mm	2.54 mm	-	2.54 mm	2.54 mm
width	34.545 mm	-	-	-	24.13 mm	34.545 mm	-	34.545 mm	34.545 mm
Other features	-	DYNAMIC BUS SIZING;UPTO 9.2 MIPS	DYNAMIC BUS SIZING;UPTO 9.2 MIPS	DYNAMIC BUS SIZING;UPTO 9.2 MIPS	-	-	DYNAMIC BUS SIZING;UPTO 9.2 MIPS	DYNAMIC BUS SIZING;UPTO 9.2 MIPS	DYNAMIC BUS SIZING;UPTO 9.2 MIPS
Maximum operating temperature	-	70 °C	70 °C	70 °C	70 °C	-	70 °C	70 °C	70 °C
Temperature level	-	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	-	COMMERCIAL	COMMERCIAL	COMMERCIAL

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