M3028 Series
SPECIFICATION FOR 5.0x7.0mm LVPECL/LVDS SMT VCXO
FEATURES
LVPECL/LVDS Differential Output
Low RMS jitter performance 12 kHz to 20 MHz
Low Phase Noise
Compliant to RoHS directive
APPLICATIONS
Base station controllers
4G/LTE applications
Ethernet, SyncE
Test and Measurement
Ordering Information:
Product
Family
Temperature Range
Code
2
6
Value
-40 °C to +85 °C
-20 °C to +70 °C
Stability*
Code
0
Code
B
U
Enable/Disable
Value
Enable High (pad 2)
No Enable/Disable
Absolute Pull
Range (APR)
Code
G
C
F
Value
±20 ppm
±25 ppm
±40 ppm
Logic Type
Code
P
L
Value
LVPECL
LVDS
Package/Lead
Configuration
Code
N
Value
Leadless
Frequency
M3028
XXX.XXXX MHz
Example: M302820BGPN 122.8800 MHz
M3028
2
* Stability is included in the APR specification.
0
B
G
P
N
122.8800MHz
LVPECL Electrical Specifications:
Parameter
Frequency of Operation
Frequency Stability
Aging
Output Type
Output Load
Symmetry (duty cycle)
Logic Level “0”
Logic Level “1”
Rise/Fall Time
Start-up Time
Enable Logic (Pad 2)
Disable Logic (Pad 2)
Control Voltage
Absolute Pull Range
Modulation Bandwidth
Input Impedance
Linearity
Operating Voltage
Supply Current
Phase Jitter (RMS)
APR
f
m
Z
in
Symbol
F
O
F/F
Min.
30
Typ.
Max.
170
Units
MHz
Conditions
Frequency Stability
See ordering information
-5
+5
-3
+3
ppm
1
st
year
Per year thereafter
RF Output
LVPECL Compatible
50
Ω
to (Vcc-2.0) V
DC
45
V
OL
V
OH
T
R
/T
F
T
SU
V
cc
-1.085
0.7
10
70% V
CC
or
N/C
30% V
CC
Frequency Adjustment
0.00
1.65
3.30
See ordering information
10
20
100
10
55
V
cc
-1.63
V
%
V
V
ns
ms
V
V
V
kHz
kΩ
%
V
mA
ps
12 KHz to 20 MHz
122.88 MHz
Revision 0
10/22/15
Page 1 of 6
The information contained herein is proprietary to MtronPTI and is submitted in confidence.
This information may not be copied or divulged without written permission from MtronPTI.
Ref. to 50% of waveform
20% to 80% of waveform
T
ambient
= +25°C
Output Enabled
Output Disabled to high-Z
Pad 1
-3 dB
Pad 1
Supply Voltage & Power Consumption
V
CC
I
CC
Φ
J
3.135
3.300
Other Parameters
0.1
3.465
80
M3028 Series
SPECIFICATION FOR 5.0x7.0mm LVPECL/LVDS SMT VCXO
LVDS Electrical Specifications:
Parameter
Frequency of Operation
Frequency Stability
Aging
Output Type
Output Load
Symmetry (duty cycle)
Differential Output
Voltage
Output Offset Voltage
Rise/Fall Time
Start-up Time
Enable Logic (Pad 2)
Disable Logic (Pad 2)
Control Voltage
Absolute Pull Range
Modulation Bandwidth
Input Impedance
Linearity
Operating Voltage
Supply Current
Phase Jitter (RMS)
APR
f
m
Z
in
Symbol
F
O
F/F
-5
-3
Min.
30
Typ.
Max.
170
Units
MHz
Conditions
Frequency Stability
See ordering information
+5
+3
ppm
1
st
year
Per year thereafter
RF Output
LVDS Compatible
100
Ω
Differential
V
OH
V
DIFF
V
OS
T
R
/T
F
T
SU
45
250
1.125
70% V
CC
or
N/C
30% V
CC
Frequency Adjustment
0.30
1.65
3.00
See ordering information
10
100
10
350
1.250
0.4
55
450
1.375
0.7
10
V
%
mV
V
ns
ms
V
V
V
kHz
kΩ
%
V
mA
ps
12 KHz to 20 MHz
156.25 MHz
Ref. to 50% of waveform
peak-to-peak differential
output voltage
20% to 80% of waveform
T
ambient
= +25°C
Output Enabled
Output Disabled to high-Z
Pad 1
-3 dB
Pad 1
Supply Voltage & Power Consumption
V
CC
I
CC
Φ
J
3.135
3.465
60
Other Parameters
0.2
3.300
Environmental & Packaging Requirements:
Storage Temperature
Mechanical Shock
Vibration
Aging
Humidity
Thermal Cycle
Hermeticity
Moisture Sensitivity Level
Solderability
Max. Soldering Conditions
Pad Termination
Package Type
-55°C to 125°C
Per MIL-STD-202, Method 213, Condition E
Per MIL-STD-202, Method 204D, Condition D
+85°C ±3°C, 720H (No BIAS)
+40°C ±2°CX90~95%, 96H (NO BIAS)
Per MIL-STD-883, Method 1011, Condition A
Per MIL-STD-202, Method 112 (1 x 10
-8
atm cc/s of Helium)
MSL1
Per EIAJ-STD-002, Method 208
See solder profile, Figure 1
Gold, 1 µm maximum thickness
6-pad 5.0 X 7.0 mm leadless ceramic. RoHS compliant.
Page 2 of 6
The information contained herein is proprietary to MtronPTI and is submitted in confidence.
This information may not be copied or divulged without written permission from MtronPTI.
M3028 Series
SPECIFICATION FOR 5.0x7.0mm LVPECL/LVDS SMT VCXO
Typical LVPECL Test Circuit & Load Circuit Diagrams:
Typical LVDS Test Circuit & Load Circuit Diagrams:
Page 3 of 6
The information contained herein is proprietary to MtronPTI and is submitted in confidence.
This information may not be copied or divulged without written permission from MtronPTI.
M3028 Series
SPECIFICATION FOR 5.0x7.0mm LVPECL/LVDS SMT VCXO
Output Waveform:
LVPECL Phase Noise Plot:
Page 4 of 6
The information contained herein is proprietary to MtronPTI and is submitted in confidence.
This information may not be copied or divulged without written permission from MtronPTI.
M3028 Series
SPECIFICATION FOR 5.0x7.0mm LVPECL/LVDS SMT VCXO
Marking, Pin Out:
Pad
1
2
3
4
5
6
Function
Control Voltage
Enable/Disable or N/C
Ground
Output
Complementary Output
+V
CC
Line 1
Line 2
Line 3
Part Marking
[part designation]
FFFMFFFF
M yy ww vv
M
F
yy
ww
vv
Legend
MtronPTI
Frequency
Year
Work Week
Factory code
Dimensions:
Page 5 of 6
The information contained herein is proprietary to MtronPTI and is submitted in confidence.
This information may not be copied or divulged without written permission from MtronPTI.
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