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AZ10LVEL33DR1

Description
Prescaler, ECL10K, PDSO8
Categorylogic    logic   
File Size191KB,8 Pages
ManufacturerArizona Microtek
Websitehttp://azmicrotek.com
Download Datasheet Parametric View All

AZ10LVEL33DR1 Overview

Prescaler, ECL10K, PDSO8

AZ10LVEL33DR1 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerArizona Microtek
package instructionSOP, SOP8,.25
Reach Compliance Codecompliant
JESD-30 codeR-PDSO-G8
JESD-609 codee0
Logic integrated circuit typePRESCALER
Number of terminals8
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP8,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
power supply-5.2 V
Certification statusNot Qualified
surface mountYES
technologyECL10K
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
ARIZONA MICROTEK, INC.
AZ10LVEL33
AZ100LVEL33
ECL/PECL
÷4
Divider
FEATURES
Operating Range of 3.0V to 5.5V
470ps Propagation Delay
4.0GHz Toggle Frequency
Internal Input Pulldown Resistors
Direct Replacement for ON Semiconductor
MC10EL33, MC100EL33 and
MC100LVEL33
Transistor Count = 91 Devices
PACKAGE
MLP 16
MLP 16
MLP 16
SOIC 8
SOIC 8 T&R
SOIC 8 T&R
SOIC 8
SOIC 8 T&R
SOIC 8 T&R
TSSOP 8
TSSOP 8 T&R
TSSOP 8 T&R
TSSOP 8
TSSOP 8 T&R
TSSOP 8 T&R
PACKAGE AVAILABILITY
PART NO.
AZ10/100LVEL33L
AZ10/100LVEL33LR1
AZ10/100LVEL33LR2
AZ10LVEL33D
AZ10LVEL33DR1
AZ10LVEL33DR2
AZ100LVEL33D
AZ100LVEL33DR1
AZ100LVEL33DR2
AZ10LVEL33T
AZ10LVEL33TR1
AZ10LVEL33TR2
AZ100LVEL33T
AZ100LVEL33TR1
AZ100LVEL33TR2
MARKING
AZML33
AZML33
AZML33
AZM10LVEL33
AZM10LVEL33
AZM10LVEL33
AZM100LVEL33
AZM100LVEL33
AZM100LVEL33
AZTLV33
AZTLV33
AZTLV33
AZHLV33
AZHLV33
AZHLV33
DESCRIPTION
The AZ10/100LVEL33 is an integrated
÷4
divider. The reset pin is asynchronous and clears the output (Q
Low, Q High) on the rising edge. Upon power-up, the internal flip-flop will be in a random logic state; the reset
¯
allows for the synchronization of multiple LVEL33’s in a system.
The LVEL33 provides a V
BB
output for single-end use or a DC bias reference for AC coupling to the device.
For single-ended input applications, the V
BB
reference should be connected to one side of the CLK/ CLK differential
¯¯¯¯
input pair. The input signal is then fed to the other CLK/ CLK input. The V
BB
pin can support 1.0mA sink/source
¯¯¯¯
current. When used, the V
BB
pin should be bypassed to ground via a 0.01µF capacitor.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
PIN DESCRIPTION
PIN
CLK, CLK
¯¯¯
Reset
V
BB
Q, Q
¯
V
CC
V
EE
FUNCTION
Clock Inputs
Asynch Reset
Reference Voltage Output
Data Outputs
Positive Supply
Negative Supply
Reset 1
8
V
CC
CLK 2
R
7
Q
÷4
CLK 3
6
Q
V
BB
4
5
V
EE
1630 S. STAPLEY DR., SUITE 125
MESA, ARIZONA 85204
USA
(480) 962-5881
FAX (480) 890-2541
www.azmicrotek.com
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