SY10E131JITR datasheet, PDF - EEWORLD Datasheet

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SY10E131JITR: DescriptionD Flip-Flop, 10E Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, ECL, PQCC28; Categorylogic logic; File Size73KB，4 Pages; ManufacturerMicrel ( Microchip ); Websitehttps://www.microchip.com

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SY10E131JITR Overview

D Flip-Flop, 10E Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, ECL, PQCC28

SY10E131JITR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Micrel ( Microchip )
package instruction	QCCJ, LDCC28,.5SQ
Reach Compliance Code	not_compliant
series	10E
JESD-30 code	S-PQCC-J28
JESD-609 code	e0
length	11.48 mm
Logic integrated circuit type	D FLIP-FLOP
Maximum Frequency@Nom-Sup	1100000000 Hz
Humidity sensitivity level	1
Number of digits	2
Number of functions	2
Number of terminals	28
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	OPEN-EMITTER
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC28,.5SQ
Package shape	SQUARE
Package form	CHIP CARRIER
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	240
power supply	-5.2 V
Maximum supply current (ICC)	70 mA
propagation delay (tpd)	0.675 ns
Certification status	Not Qualified
Maximum seat height	4.57 mm
surface mount	YES
technology	ECL
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
Trigger type	POSITIVE EDGE
width	11.48 mm
minfmax	1100 MHz

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4-BIT D

FLIP-FLOP

SY10E131

SY100E131

FEATURES

1100MHz min. toggle frequency

Extended 100E V

range of –4.2V to –5.5V

Differential output

Individual and common clocks

Indivldual asynchronous reset

Paired asynchronous sets

DESCRIPTION

The SY10/100E131 are high-speed quad master slave

D-type flip-flops with differential outputs designed for use

in new, high-performance ECL systems. The flip-flops may

be individually clocked by holding C

(Common Clock) at

a logic LOW and then using the four individual CE (Clock

Enable CE

–CE

) inputs to accomplish such clocking.

Alternatively, all four flip-flops can be clocked in common

by holding the CE inputs LOW and then using C

to clock

the data. In the common clock mode, the CE input acts as

a control that passes the C

signal to the flip-flop. Data is

clocked into the flip-flop on the rising edge of the output of

the logical OR operation between CE and C

(data enters

the master when both C

and CE are LOW and data

transfers to the slave when either CE or C

or both, go

HIGH).

Asynchronous set and reset controls are provided. The

reset controls are individual and the set controls are

pairwise.

Fully compatible with Industry standard 10KH,

100K ECL levels

Internal 75K

Ω

input pulldown resistors

Fully compatible with Motorola MC10E/100E131

Available in 28-pin PLCC package

PIN CONFIGURATION

CCO

PIN NAMES

Function

Data Inputs

Clock Enables (Individual)

Resets

Common Clock

Sets (paired)

True Outputs

Inverting Outputs

to Output

-D

-CE

25 24 23 22 21 20 19

-R

10 11

, S

-Q

CCO

PLCC

TOP VIEW

J28-1

CCO

Rev.: E

Amendment: /0

Issue Date: November, 1998

SY10E131JITR Related Products

	SY10E131JITR	SY100E131JCTR
Description	D Flip-Flop, 10E Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, ECL, PQCC28	D Flip-Flop, 100E Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, ECL, PQCC28, PLASTIC, LCC-28
Is it Rohs certified?	incompatible	incompatible
Maker	Micrel ( Microchip )	Micrel ( Microchip )
package instruction	QCCJ, LDCC28,.5SQ	QCCJ, LDCC28,.5SQ
Reach Compliance Code	not_compliant	not_compliant
series	10E	100E
JESD-30 code	S-PQCC-J28	S-PQCC-J28
JESD-609 code	e0	e0
length	11.48 mm	11.48 mm
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP
Maximum Frequency@Nom-Sup	1100000000 Hz	1100000000 Hz
Humidity sensitivity level	1	1
Number of digits	2	2
Number of functions	2	2
Number of terminals	28	28
Maximum operating temperature	85 °C	85 °C
Output characteristics	OPEN-EMITTER	OPEN-EMITTER
Output polarity	COMPLEMENTARY	COMPLEMENTARY
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	QCCJ
Encapsulate equivalent code	LDCC28,.5SQ	LDCC28,.5SQ
Package shape	SQUARE	SQUARE
Package form	CHIP CARRIER	CHIP CARRIER
method of packing	TAPE AND REEL	TAPE AND REEL
Peak Reflow Temperature (Celsius)	240	240
power supply	-5.2 V	-4.5 V
Maximum supply current (ICC)	70 mA	81 mA
propagation delay (tpd)	0.675 ns	0.675 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	4.57 mm	4.57 mm
surface mount	YES	YES
technology	ECL	ECL
Temperature level	INDUSTRIAL	COMMERCIAL EXTENDED
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
Terminal form	J BEND	J BEND
Terminal pitch	1.27 mm	1.27 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	30	30
Trigger type	POSITIVE EDGE	POSITIVE EDGE
width	11.48 mm	11.48 mm
minfmax	1100 MHz	1100 MHz

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