MC10171
Dual Binary to 1-4 Decoder
(Low)
The MC10171 is a binary coded 2 line to dual 4 line decoder with
selected outputs low. With either E0 or E1 high, the corresponding
selected 4 outputs are high. The common enable E, when high, forces
all outputs high.
•
P
D
= 325 mW typ/pkg (No Load)
•
t
pd
= 4.0 ns typ
•
t
r
, t
f
= 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
E0 14
10 Q0 3
11 Q0 2
12 Q0 1
A9
13 Q0 0
3 Q1 3
B7
4 Q1 2
E 15
E1 2
V
CC1
= PIN 1
V
CC2
= PIN 16
V
EE
= PIN 8
5 Q1 1
6 Q1 0
A
WL
YY
WW
PLCC–20
FN SUFFIX
CASE 775
PDIP–16
P SUFFIX
CASE 648
1
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MARKING
DIAGRAMS
16
CDIP–16
L SUFFIX
CASE 620
1
16
MC10171P
AWLYYWW
1
10171
AWLYYWW
MC10171L
AWLYYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
DIP PIN ASSIGNMENT
V
CC1
E1
OUTPUTS
Q13
Q01
H
L
H
H
H
H
H
Q02
H
H
L
H
H
H
H
Q03
H
H
H
L
H
H
H
Q12
Q11
Q10
B
V
EE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC2
E
E0
Q00
Q01
Q02
Q03
A
TRUTH TABLE
ENABLE INPUTS
E
L
L
L
L
L
L
H
E0
L
L
L
L
L
H
X
E1
L
L
L
L
H
L
X
INPUTS
A
L
L
H
H
L
L
X
B
L
H
L
H
L
L
X
Q10
L
H
H
H
H
L
H
Q11
H
L
H
H
H
H
H
Q12
H
H
L
H
H
H
H
Q13
H
H
H
L
H
H
H
Q00
L
H
H
H
L
H
H
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).
ORDERING INFORMATION
Device
MC10171L
MC10171P
MC10171FN
Package
CDIP–16
PDIP–16
PLCC–20
Shipping
25 Units / Rail
25 Units / Rail
46 Units / Rail
©
Semiconductor Components Industries, LLC, 2002
1
January, 2002 – Rev. 7
Publication Order Number:
MC10171/D
MC10171
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Under
Test
8
14
14
6
13
13
6
13
6
13
0.5
–1.060
–1.060
–1.890
–1.080
–1.080
–1.655
–1.655
–0.890
–0.890
–1.675
–30°C
Min
Max
85
350
0.5
–0.960
–0.960
–1.850
–0.980
–0.980
–1.630
–1.630
–0.810
–0.810
–1.650
Min
+25°C
Typ
65
Max
77
220
0.3
–0.890
–0.890
–1.825
–0.910
–0.910
–1.595
–1.595
–0.700
–0.700
–1.615
Min
+85°C
Max
85
220
Unit
mAdc
µAdc
µAdc
Vdc
Vdc
Vdc
Vdc
ns
t
7+6+
t
7–6–
t
7+13+
t
7–13–
t
6+
t
13+
t
6–
t
13–
6
6
13
13
6
13
6
13
1.5
1.5
1.5
1.5
1.0
1.0
1.0
1.0
6.2
6.2
6.2
6.2
3.3
3.3
3.3
3.3
1.5
1.5
1.5
1.5
1.1
1.1
1.1
1.1
4.0
4.0
4.0
4.0
2.0
2.0
2.0
2.0
6.0
6.0
6.0
6.0
3.3
3.3
3.3
3.3
1.5
1.5
1.5
1.5
1.1
1.1
1.1
1.1
6.4
6.4
6.4
6.4
3.4
3.4
3.4
3.4
Characteristic
Power Supply Drain Current
Input Current
Symbol
I
E
I
inH
I
inL
Output Voltage
Output Voltage
Threshold Voltage
Threshold Voltage
Logic 1
Logic 0
Logic 1
Logic 0
V
OH
V
OL
V
OHA
V
OLA
Switching Times (50Ω Load)
Propagation Delay
Rise Time
Fall Time
(20 to 80%)
(20 to 80%)
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2
MC10171
ELECTRICAL CHARACTERISTICS
(continued)
TEST VOLTAGE VALUES
(Volts)
@ Test Temperature
–30°C
+25°C
+85°C
Pin
Under
Test
8
14
14
6
13
13
6
13
6
13
2,9,14,15
2,7,14,15
+0.31V
t
7+6+
t
7–6–
t
7+13+
t
7–13–
(20 to 80%)
(20 to 80%)
t
6+
t
13+
t
6–
t
13–
6
6
13
13
6
13
6
13
2,9,14,15
2,9,14,15
2,9,14,15
2,9,14,15
Pulse In
7
7
7
7
7
7
7
7
15
15
2,7,9,14,15
15
15
7
9
Pulse Out
6
6
13
13
6
13
6
13
V
IHmax
–0.890
–0.810
–0.700
V
ILmin
–1.890
–1.850
–1.825
V
IHAmin
–1.205
–1.105
–1.035
V
ILAmax
–1.500
–1.475
–1.440
V
EE
–5.2
–5.2
–5.2
(V
CC
)
Gnd
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
+2.0 V
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
V
IHmax
2,7,9,14,15
14
14
V
ILmin
V
IHAmin
V
ILAmax
V
EE
8
8
8
8
8
8
8
8
8
8
–3.2 V
8
8
8
8
8
8
8
8
Characteristic
Power Supply Drain Current
Input Current
Symbol
I
E
I
inH
I
inL
Output Voltage
Output Voltage
Threshold Voltage
Threshold Voltage
Switching Times
Propagation Delay
Logic 1
Logic 0
Logic 1
Logic 0
(50Ω Load)
V
OH
V
OL
V
OHA
V
OLA
Rise Time
Fall Time
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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3
MC10171
PACKAGE DIMENSIONS
PLCC–20
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
B
–N–
Y BRK
D
–L–
–M–
W
D
X
V
A
Z
R
0.007 (0.180)
0.007 (0.180)
M
0.007 (0.180)
U
M
T L-M
M
S
N
S
S
0.007 (0.180)
T L-M
N
S
Z
20
1
G1
0.010 (0.250)
S
T L-M
S
N
S
VIEW D–D
T L-M
T L-M
S
N
N
S
H
0.007 (0.180)
M
T L-M
S
N
S
M
S
S
K1
K
C
E
0.004 (0.100)
G
G1
0.010 (0.250)
S
T L-M
J
–T–
SEATING
PLANE
F
VIEW S
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
0.007 (0.180)
M
T L-M
S
N
S
VIEW S
S
N
S
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.385
0.395
0.385
0.395
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
---
0.025
---
0.350
0.356
0.350
0.356
0.042
0.048
0.042
0.048
0.042
0.056
---
0.020
2
_
10
_
0.310
0.330
0.040
---
MILLIMETERS
MIN
MAX
9.78
10.03
9.78
10.03
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
---
0.64
---
8.89
9.04
8.89
9.04
1.07
1.21
1.07
1.21
1.07
1.42
---
0.50
2
_
10
_
7.88
8.38
1.02
---
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4
MC10171
PACKAGE DIMENSIONS
CDIP–16
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE T
–A–
16
9
–B–
1
8
C
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
DIM
A
B
C
D
E
F
G
H
K
L
M
N
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
---
0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0
_
15
_
0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
---
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0
_
15
_
0.51
1.01
–T–
SEATING
PLANE
N
E
F
D
G
16 PL
K
M
J
16 PL
0.25 (0.010)
M
M
T B
S
0.25 (0.010)
T A
S
–A–
16
9
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
B
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0
_
10
_
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0
_
10
_
0.51
1.01
F
S
C
L
–T–
H
G
D
16 PL
SEATING
PLANE
K
J
T A
M
M
0.25 (0.010)
M
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