EP610DI-15 datasheet, PDF - EEWORLD Datasheet

EP610DI-15: DescriptionUV PLD, 15ns, CDIP24, WINDOWED, CERDIP-24; CategoryProgrammable logic devices Programmable logic; File Size279KB，11 Pages; ManufacturerAltera (Intel)

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EP610DI-15 Overview

UV PLD, 15ns, CDIP24, WINDOWED, CERDIP-24

Parameter Name	Attribute value
Maker	Altera (Intel)
Parts packaging code	DIP
package instruction	WINDOWED, CERDIP-24
Contacts	24
Reach Compliance Code	unknown
maximum clock frequency	83.3 MHz
JESD-30 code	R-GDIP-T24
Dedicated input times	4
Number of I/O lines	16
Number of terminals	24
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	4 DEDICATED INPUTS, 16 I/O
Output function	MACROCELL
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Programmable logic type	UV PLD
propagation delay	15 ns
Certification status	Not Qualified
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
Temperature level	INDUSTRIAL
Terminal form	THROUGH-HOLE
Terminal location	DUAL

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

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