4 Mbit (x16) Multi-Purpose Flash
SST39WF400B
Data Sheet
FEATURES:
• Organized as 256K x16
• Single Voltage Read and Write Operations
– 1.65-1.95V
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 5 mA (typical)
– Standby Current: 5 µA (typical)
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Block-Erase Capability
– Uniform 32 KWord blocks
• Fast Read Access Time
– 70 ns
• Latched Address and Data
• Fast Erase and Word-Program
– Sector-Erase Time: 36 ms (typical)
– Block-Erase Time: 36 ms (typical)
– Chip-Erase Time: 140 ms (typical)
– Word-Program Time: 28 µs (typical)
• Automatic Write Timing
– Internal V
PP
Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 48-ball TFBGA (6mm x 8mm)
– 48-ball WFBGA (4mm x 6mm) Micro-Package
– 48-ball XFLGA (4mm x 6mm) Micro-Package
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST39WF400B is a 256K x16 CMOS Multi-Purpose
Flash (MPF) manufactured with SST proprietary, high-per-
formance CMOS SuperFlash technology. The split-gate
cell design and thick-oxide tunneling injector attain better
reliability and manufacturability compared to alternate
approaches. The SST39WF400B writes (Program or
Erase) with a 1.65-1.95V power supply. This device con-
forms to JEDEC standard pin assignments for x16 memo-
ries.
The SST39WF400B features high-performance Word-Pro-
gramming which provides a typical Word-Program time of
28 µsec. It uses Toggle Bit or Data# Polling to detect the
completion of the Program or Erase operation. On-chip
hardware and software data protection schemes protect
against inadvertent writes. Designed, manufactured, and
tested for a wide spectrum of applications, the
SST39WF400B is offered with a guaranteed typical endur-
ance of 100,000 cycles. Data retention is rated at greater
than 100 years.
The SST39WF400B is suited for applications that require
convenient and economical updating of program, configu-
ration, or data memory. For all system applications, this
MPF significantly improves performance and reliability,
while lowering power consumption. It inherently uses less
©2010 Silicon Storage Technology, Inc.
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energy during Erase and Program than alternative flash
technologies. When programming a flash device, the total
energy consumed is a function of the applied voltage, cur-
rent, and time of application. For any given voltage range,
SuperFlash technology uses less current to program and
has a shorter erase time; therefore, the total energy con-
sumed during any Erase or Program operation is less than
alternative flash technologies. These devices also improve
flexibility while lowering the cost for program, data, and con-
figuration storage applications.
SuperFlash technology provides fixed Erase and Program
times independent of the number of Erase/Program cycles
that have occurred. Consequently, the system software or
hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To meet surface mount requirements, the SST39WF400B
is offered in 48-ball TFBGA, 48-ball WFBGA, and a 48-ball
XFLGA packages. See Figures 2 and 3 for pin assign-
ments and Table 2 for pin descriptions.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
4 Mbit (x16) Multi-Purpose Flash
SST39WF400B
Data Sheet
Device Operation
Commands, which are used to initiate the memory opera-
tion functions of the device, are written to the device using
standard microprocessor write sequences. A command is
written by asserting WE# low while keeping CE# low. The
address bus is latched on the falling edge of WE# or CE#,
whichever occurs last. The data bus is latched on the rising
edge of WE# or CE#, whichever occurs first.
Sector-/Block-Erase Operation
The SST39WF400B offers both Sector-Erase and Block-
Erase modes which allow the system to erase the device
on a sector-by-sector, or block-by-block, basis.
The sector architecture is based on an uniform sector size
of 2 KWord. Initiate the Sector-Erase operation by execut-
ing a six-byte command sequence with Sector-Erase com-
mand (30H) and sector address (SA) in the last bus cycle.
The Block-Erase mode is based on an uniform block size
of 32 KWord. Initiate the Block-Erase operation by execut-
ing a six-byte command sequence with Block-Erase com-
mand (50H) and block address (BA) in the last bus cycle.
The sector or block address is latched on the falling edge of
the sixth WE# pulse, while the command (30H or 50H) is
latched on the rising edge of the sixth WE# pulse. The
internal Erase operation begins after the sixth WE# pulse.
The End-of-Erase operation can be determined using
either Data# Polling or Toggle Bit methods. See Figures 10
and 11 for timing waveforms. Any commands issued during
the Sector- or Block-Erase operation are ignored.
Read
The Read operation of the SST39WF400B is controlled by
CE# and OE#; both have to be low for the system to obtain
data from the outputs.
CE# is used for device selection. When CE# is high, the
chip is deselected and only standby power is consumed.
OE# is the output control and is used to gate data from the
output pins. The data bus is in high impedance state when
either CE# or OE# is high. See Figure 5.
Word-Program Operation
The SST39WF400B is programmed on a word-by-word
basis. The sector where the word exists must be fully
erased before programming.
Programming is accomplished in three steps:
1. Load the three-byte sequence for Software Data
Protection.
2. Load word address and word data. During the
Word-Program operation, the addresses are
latched on the falling edge of either CE# or WE#,
whichever occurs last. The data is latched on the
rising edge of either CE# or WE#, whichever
occurs first.
3. Initiate the internal Program operation after the
rising edge of the fourth WE# or CE#, whichever
occurs first. Once initiated, the Program operation
will be completed within 40 µs. See Figures 6 and
7 for WE# and CE# controlled Program operation
timing diagrams and Figure 17 for flowcharts.
During the Program operation, the only valid reads are
Data# Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any
commands issued during the internal Program operation
are ignored.
Chip-Erase Operation
The SST39WF400B provides a Chip-Erase operation,
which allows the user to erase the entire memory array to
the ‘1’ state. This is useful when the entire device must be
quickly erased.
Initiate the Chip-Erase operation by executing a six-byte
command sequence with Chip-Erase command (10H) at
address 5555H in the last byte sequence.
The Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 4 for the command sequence, Figure 9 for the
timing diagram, and Figure 20 for the flowchart. Any com-
mands issued during the Chip-Erase operation are
ignored.
©2010 Silicon Storage Technology, Inc.
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4 Mbit (x16) Multi-Purpose Flash
SST39WF400B
Data Sheet
Write Operation Status Detection
To optimize the system write cycle time, the
SST39WF400B provides two software means to detect the
completion of a Program or Erase write cycle. The software
detection includes two status bits—Data# Polling (DQ
7
)
and Toggle Bit (DQ
6
). The End-of-Write detection mode is
enabled after the rising edge of WE#, which initiates the
internal Program or Erase operation.
The completion of the nonvolatile Write is asynchronous
with the system; therefore, either a Data# Polling or Toggle
Bit read may occur simultaneously with the completion of
the Write cycle. If this occurs, the system may get an erro-
neous result, i.e., valid data may appear to conflict with
either DQ
7
or DQ
6
. To prevent spurious rejection in the
event of an erroneous result, the software routine must
include a loop to read the accessed location an additional
two (2) times. If both Reads are valid, then the device has
completed the Write cycle, otherwise the rejection is valid.
The Toggle Bit is valid after the rising edge of fourth WE#
(or CE#) pulse for Program operation. For Sector-, Block-
or Chip-Erase, the Toggle Bit is valid after the rising edge of
sixth WE# (or CE#) pulse. See Figure 0-1 for Toggle Bit
timing diagram and Figure 18 for a flowchart.
Data Protection
The SST39WF400B provides both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.0V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Data# Polling (DQ
7
)
When the SST39WF400B is in the internal Program oper-
ation, any attempt to read DQ
7
will produce the comple-
ment of the true data. Once the Program operation is
complete, DQ
7
will produce true data.
Although DQ
7
may have valid data immediately following
the completion of an internal Write operation, the remain-
ing data outputs may still be invalid. Valid data on the
entire data bus will appear in subsequent successive
Read cycles after an interval of 1 µs. During an internal
Erase operation, any attempt to read DQ
7
will produce a
‘0’. Once the internal Erase operation is complete, DQ
7
will
produce a ‘1’.
The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block-, or Chip-Erase, the Data# Polling is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 8 for
Data# Polling timing diagram and Figure 18 for a flowchart.
Software Data Protection (SDP)
The SST39WF400B provides the JEDEC approved Soft-
ware Data Protection scheme for all data alteration opera-
tions, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. This group of devices are shipped with
the Software Data Protection permanently enabled. See
Table 4 for the specific software command codes. During
SDP command sequence, invalid commands will abort the
device to Read mode within T
RC
. The contents of DQ
15
-
DQ
8
can be V
IL
or V
IH
, but no other value, during any SDP
command sequence.
Common Flash Memory Interface (CFI)
The SST39WF400B contains the CFI information that
describes the characteristics of the device, and supports
both the original SST CFI Query mode implementation for
compatibility with existing SST devices, as well as the gen-
eral CFI Query mode.
To enter the SST CFI Query mode, the system must write
the three-byte sequence, same as the Product ID Entry
command, with 98H (CFI Query command) to address
5555H in the last byte sequence.
Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating ‘1’s
and ‘0’s, i.e., toggling between ‘1’ and ‘0’.
When the Program or Erase operation is complete, the
DQ
6
bit will stop toggling and the device is ready for the
next operation.
©2010 Silicon Storage Technology, Inc.
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4 Mbit (x16) Multi-Purpose Flash
SST39WF400B
Data Sheet
To enter the general CFI Query mode, the system must
write a one-byte sequence using the Entry command with
98H to address 55H.
Once the device enters the CFI Query mode, the system
can read CFI data at the addresses given in Tables 5
through 7. The system must write the CFI Exit command to
return to Read mode from the CFI Query mode.
Product Identification Mode Exit/
CFI Mode Exit
To return to the standard Read mode, exit the Software
Product Identification mode by issuing the Software ID Exit
command sequence.
The Software ID Exit command can reset the
SST39WF400B to the Read mode after an inadvertent
transient condition that causes the device to behave abnor-
mally.
The Software ID Exit/CFI Exit command is ignored during
an internal Program or Erase operation. See Table 4 for
software command codes, Figure 14 for timing waveform,
and Figure 19 for a flowchart.
Product Identification
The Product Identification mode identifies the device as the
SST39WF400B and the manufacturer as SST. This mode
is accessed by software operations. Use the Software
Product Identification operation to identify the part (i.e.,
using the device ID) when using multiple manufacturers in
the same socket. For details, see Table 4 for software
operation, Figure 12 for the Software ID Entry and Read
timing diagram, and Figure 19 for the Software ID Entry
command sequence flowchart.
TABLE 1: Product Identification Table
Address
Manufacturer’s ID
Device ID
SST39WF400B
0001H
272EH
T1.0 1370
Data
00BFH
0000H
©2010 Silicon Storage Technology, Inc.
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4 Mbit (x16) Multi-Purpose Flash
SST39WF400B
Data Sheet
X-Decoder
SuperFlash
Memory
Memory Address
Address Buffer & Latches
Y-Decoder
CE#
OE#
WE#
DQ15 - DQ0
1370 B1.0
Control Logic
I/O Buffers and Data Latches
FIGURE 1: Functional Block Diagram
TOP VIEW (balls facing down)
SST39WF400B
6
A2
A4
A3
A5
A6
A7
NC
A17
NC
NC
NC
WE#
NC
NC
A9
A10
A8
A11
A13
A12
A14
A15
5
A1
4
A0
3
CE#
DQ8 DQ10
OE# DQ9
NC
NC
DQ4 DQ11 A16
DQ5 DQ6 DQ7
2
V
SS
1
DQ0 DQ1 DQ2 DQ3
V
DD
DQ12 DQ13 DQ14 DQ15 V
SS
A
B
C
D
E
F
G
H
J
K
L
1370 48-wfbga M2Q P02.0
FIGURE 2: Pin Assignments for 48-Ball WFBGA and 48-Ball XFLGA
©2010 Silicon Storage Technology, Inc.
S71370-02-000
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