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Datasheet> All Categories > storage> storage> CAT140081TWI-GT3
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CAT140081TWI-GT3

Description
Voltage Supervisor with I2C Serial CMOS EEPROM
Categorystorage    storage   
File Size137KB，11 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
Environmental Compliance
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CAT140081TWI-GT3 Overview

Voltage Supervisor with I2C Serial CMOS EEPROM

CAT140081TWI-GT3 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerON Semiconductor
Parts packaging codeSOIC
package instruction0.150 INCH, HALOGEN FREE AND ROHS COMPLIANT, MS-012, SOIC-8
Contacts8
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum clock frequency (fCLK)0.4 MHz
Data retention time - minimum100
Durability1000000 Write/Erase Cycles
I2C control byte1010DMMR
JESD-30 codeR-PDSO-G8
JESD-609 codee4
length4.9 mm
memory density8192 bit
Memory IC TypeEEPROM
memory width1
Number of functions1
Number of terminals8
word count8192 words
character code8000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize8KX1
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP8,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialSERIAL
Peak Reflow Temperature (Celsius)260
power supply3/5 V
Programming voltage3 V
Certification statusNot Qualified
Maximum seat height1.75 mm
Serial bus typeI2C
Maximum standby current0.000017 A
Maximum slew rate0.001 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)2.5 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceNICKEL PALLADIUM GOLD
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
width3.9 mm
Maximum write cycle time (tWC)5 ms
write protectSOFTWARE
Base Number Matches1

CAT140081TWI-GT3 Preview

CAT140xx
Voltage Supervisor with I
2
C
Serial CMOS EEPROM
Description
The CAT140xx (see table below) are memory and supervisory
solutions for microcontroller based systems. A CMOS serial
EEPROM memory and a system power supervisor with brown−out
protection are integrated together. Memory interface is via both the
standard (100 kHz) as well as fast (400 kHz) I
2
C protocol.
The CAT140xx provides a precision V
CC
sense circuit with two
reset output options: CMOS active low output or CMOS active high.
The RESET output is active whenever V
CC
is below the reset
threshold or falls below the reset threshold voltage.
The power supply monitor and reset circuit protect system
controllers during power up/down and against brownout conditions.
Seven reset threshold voltages support 5 V, 3.3 V, 3 V and 2.5 V
systems. If power supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller, ASIC or
peripherals from operating. Reset signals become inactive typically
240 ms after the supply voltage exceeds the reset threshold level.
Features
♦
http://onsemi.com
SOIC−8
CASE 751BD
PIN CONFIGURATION
CAT
14016 / 08 / 04 / 02
NC / NC / NC / A
0
NC / NC / A
1
/ A
1
NC / A
2
/ A
2
/ A
2
V
SS
1
2
3
4
SOIC (W)
8
7
6
5
V
CC
RST/RST
SCL
SDA
•
Precision Power Supply Voltage Monitor
•
•
•
•
•
•
•
•
•
5 V, 3.3 V, 3 V and 2.5 V Systems
♦
7 Threshold Voltage Options
Active High or Low Reset
♦
Valid Reset Guaranteed at V
CC
= 1 V
Supports Standard and Fast I
2
C Protocol
16−Byte Page Write Buffer
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial Temperature Range
RoHS−Compliant 8−Pin SOIC Package
These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
PIN FUNCTION
Pin Name
A0, A1, A2
SDA
SCL
RST/RST
V
CC
V
SS
NC
Function
Device Address Inputs
Serial Data Input/Output
Serial Clock Input
Reset Output
Power Supply
Ground
No Connect
MEMORY SIZE SELECTOR
Product
14002
14004
14008
14016
Memory Density
2−Kbit
4−Kbit
8−Kbit
16−Kbit
THRESHOLD SUFFIX SELECTOR
Nominal Threshold Voltage
4.63 V
4.38 V
4.00 V
3.08 V
2.93 V
2.63 V
2.32 V
Threshold Suffix
Designation
L
M
J
T
S
R
Z
ORDERING INFORMATION
For Ordering Information details, see page 10.
©
Semiconductor Components Industries, LLC, 2011
November, 2011
−
Rev. 3
1
Publication Order Number:
CAT14002/D
CAT140xx
BLOCK DIAGRAM
V
CC
SDA
SCL
A0
A1
A2
EEPROM
VOLTAGE
DETECTOR
RST or RST
V
SS
SPECIFICATIONS
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Storage Temperature
Voltage on Any Pin with Respect to Ground (Note 1)
Ratings
–65 to +150
−0.5
to +6.5
Units
°C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than
−0.5
V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than
−1.5
V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS
(Note 2)
Symbol
NEND (Note 3)
TDR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V
CC
= 5 V, 25°C
Table 3. D.C. OPERATING CHARACTERISTICS
V
CC
= +2.5 V to +5.5 V, unless otherwise specified.
Symbol
I
CC
I
SB
I
L
V
IL
V
IH
V
OL
Parameter
Supply Current
Standby Current
Test Conditions
Read or Write at 400 kHz
V
CC
< 5.5 V; All I/O Pins at V
SS
or V
CC
V
CC
< 3.6 V; All I/O Pins at V
SS
or V
CC
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
SDA
V
CC
≥
2.5 V, I
OL
= 3.0 mA
Pin at GND or V
CC
−0.5
V
CC
x 0.7
10
8
Min
Typ
Max
1
22
17
2
V
CC
x 0.3
V
CC
+ 0.5
0.4
mA
V
V
V
Units
mA
mA
http://onsemi.com
2
CAT140xx
Table 4. A.C. CHARACTERISTICS (MEMORY)
(Note 1)
V
CC
= 2.5 V to 5.5 V, T
A
=
−40°C
to 85°C, unless otherwise specified.
Standard
Symbol
F
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
(Note 2)
t
F
(Note 2)
t
SU:STO
t
BUF
t
AA
t
DH
T
I
(Note 2)
t
WR
t
PU
(Notes 2 & 3)
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
Noise Pulse Filtered at SCL and SDA Inputs
Write Cycle Time
Power−up to Ready Mode
100
100
5
1
4
4.7
3.5
100
100
5
1
4
4.7
4
4.7
0
250
1000
300
0.6
1.3
0.9
Parameter
Min
Max
100
0.6
1.3
0.6
0.6
0
100
300
300
Min
Fast
Max
400
Units
kHz
ms
ms
ms
ms
ms
ns
ns
ns
ms
ms
ms
ns
ns
ms
ms
1. Test conditions according to “A.C. Test Conditions” table.
2. Tested initially and after a design or process change that affects this parameter.
3. t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
Table 5. A.C. TEST CONDITIONS
Parameter
Input Levels
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
Output Load
Test Conditions
0.2 x V
CC
to 0.8 x V
CC
≤50
ns
0.3 x V
CC
, 0.7 x V
CC
0.5 x V
CC
Current Source: I
OL
= 3 mA; C
L
= 100 pF
http://onsemi.com
3
CAT140xx
Table 6. ELECTRICAL CHARACTERISTICS (SUPERVISORY FUNCTION)
V
CC
= Full range, T
A
=
−40°C
to +85°C unless otherwise noted. Typical values at T
A
= +25°C and V
CC
= 5 V for L/M/J versions,
V
CC
= 3.3 V for T/S versions, V
CC
= 3 V for R version and V
CC
= 2.5 V for Z version.
Symbol
V
TH
Parameter
Reset Threshold
Voltage
Threshold
L
T
A
= +25°C
T
A
=
−40°C
to +85°C
M
T
A
= +25°C
T
A
=
−40°C
to +85°C
J
T
A
= +25°C
T
A
=
−40°C
to +85°C
T
T
A
= +25°C
T
A
=
−40°C
to +85°C
S
T
A
= +25°C
T
A
=
−40°C
to +85°C
R
T
A
= +25°C
T
A
=
−40°C
to +85°C
Z
T
A
= +25°C
T
A
=
−40°C
to +85°C
Symbol
Parameter
Reset Threshold Tempco
t
RPD
t
PURST
V
OL
V
CC
to Reset Delay (Note 2)
Reset Active Timeout Period
RESET Output Voltage Low
(Push−pull, Active LOW,
CAT140xx9)
V
CC
= V
TH
to (V
TH
−100
mV)
T
A
=
−40°C
to +85°C
V
CC
= V
TH
min, I
SINK
= 1.2 mA
R/S/T/Z
V
CC
= V
TH
min, I
SINK
= 3.2 mA
J/L/M
V
CC
> 1.0 V, I
SINK
= 50
mA
V
OH
RESET Output Voltage High
(Push−pull, Active LOW,
CAT140xx9)
V
CC
= V
TH
max, I
SOURCE
=
−500
mA
R/S/T/Z
V
CC
= V
TH
max, I
SOURCE
=
−800
mA
J/L/M
V
CC
> V
TH
max, I
SINK
= 1.2 mA
R/S/T/Z
V
CC
> V
TH
max, I
SINK
= 3.2 mA
J/L/M
1.8 V < V
CC
≤
V
TH
min,
I
SOURCE
=
−150
mA
0.8 V
CC
0.8 V
CC
V
CC
−
1.5
0.3
0.4
V
V
140
Conditions
Conditions
Min
4.56
4.50
4.31
4.25
3.93
3.89
3.04
3.00
2.89
2.85
2.59
2.55
2.28
2.25
Min
Typ
(Note 1)
30
20
240
460
0.3
0.4
0.3
V
2.32
2.63
2.93
3.08
4.00
4.38
Typ
4.63
Max
4.70
4.75
4.45
4.50
4.06
4.10
3.11
3.15
2.96
3.00
2.66
2.70
2.35
2.38
Max
Units
ppm/°C
ms
ms
V
Units
V
V
OL
RESET Output Voltage Low
(Push−pull, Active HIGH,
CAT140xx1)
V
OH
RESET Output Voltage High
(Push−pull, Active HIGH,
CAT140xx1)
1. Production testing done at T
A
= +25°C; limits over temperature guaranteed by design only.
2. RESET output for the CAT140xx9; RESET output for the CAT140xx1.
http://onsemi.com
4
CAT140xx
PIN DESCRIPTION
RESET/RESET:
RESET OUTPUT
This output is available in two versions: CMOS Active Low
(CAT140xx9) and CMOS Active High (CAT140xx1). Both
versions are push−pull outputs for high efficiency.
SDA:
SERIAL DATA ADDRESS
The Serial Data I/O pin receives input data and transmits
data stored in EEPROM. In transmit mode, this pin is open
drain. Data is acquired on the positive edge, and is delivered
on the negative edge of SCL.
SCL:
SERIAL CLOCK
The Serial Clock input pin accepts the Serial Clock
generated by the Master.
A0, A1, A2:
Device Address Inputs
The Address inputs set the device address when cascading
multiple devices. When not driven, these pins are pulled
LOW internally.
DEVICE OPERATION
The CAT140xx products combine the accurate voltage
monitoring capabilities of a standalone voltage supervisor
with the high quality and reliability of standard EEPROMs
from ON Semiconductor.
Reset Controller Description
initial voltage of 0.5 V above the threshold and drops below
it by the amplitude of the overdrive voltage (V
TH
−
V
CC
).
TRANSIENT DURATION [μs]
T
AMB
= 25ºC
The reset signal is asserted LOW for the CAT140xx9 and
HIGH for the CAT140xx1 when the power supply voltage
falls below the threshold trip voltage and remains asserted
for at least 140 ms (t
PURST
) after the power supply voltage
has risen above the threshold. Reset output timing is shown
in Figure 2.
The CAT140xx devices protect
mPs
against brownout
failure. Short duration V
CC
transients of 4
msec
or less and
100 mV amplitude typically do not generate a Reset pulse.
Figure 1 shows the maximum pulse duration of
negative−going V
CC
transients that do not cause a reset
condition. As the amplitude of the transient goes further
below the threshold (increasing V
TH
−
V
CC
), the maximum
pulse duration decreases. In this test, the V
CC
starts from an
CAT140xxZ
CAT140xxM
RESET OVERDRIVE V
TH
- V
CC
[mV]
Figure 1. Maximum Transient Duration without
Causing a Reset Pulse vs. Overdrive Voltage
V
TH
V
CC
V
RVALID
t
PURST
t
RPD
t
PURST
t
RPD
RESET
CAT140xx9
RESET
CAT140xx1
Figure 2. RESET Output Timing
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