EE PLD, 12ns, 512-Cell, CMOS, PBGA256, THERMALLY ENHANCED, FBGA-256
| Parameter Name | Attribute value |
| Is it lead-free? | Contains lead |
| Is it Rohs certified? | incompatible |
| Maker | Lattice |
| Parts packaging code | BGA |
| package instruction | THERMALLY ENHANCED, FBGA-256 |
| Contacts | 256 |
| Reach Compliance Code | compliant |
| ECCN code | EAR99 |
| Other features | YES |
| maximum clock frequency | 56 MHz |
| In-system programmable | YES |
| JESD-30 code | S-PBGA-B256 |
| JESD-609 code | e0 |
| JTAG BST | YES |
| length | 17 mm |
| Humidity sensitivity level | 3 |
| Dedicated input times | |
| Number of I/O lines | 192 |
| Number of macro cells | 512 |
| Number of terminals | 256 |
| Maximum operating temperature | 85 °C |
| Minimum operating temperature | -40 °C |
| organize | 0 DEDICATED INPUTS, 192 I/O |
| Output function | MACROCELL |
| Package body material | PLASTIC/EPOXY |
| encapsulated code | BGA |
| Encapsulate equivalent code | BGA256,16X16,40 |
| Package shape | SQUARE |
| Package form | GRID ARRAY |
| Peak Reflow Temperature (Celsius) | 225 |
| power supply | 2.5/3.3,3.3 V |
| Programmable logic type | EE PLD |
| propagation delay | 12 ns |
| Certification status | Not Qualified |
| Maximum seat height | 2.1 mm |
| Maximum supply voltage | 3.6 V |
| Minimum supply voltage | 3 V |
| Nominal supply voltage | 3.3 V |
| surface mount | YES |
| technology | CMOS |
| Temperature level | INDUSTRIAL |
| Terminal surface | Tin/Lead (Sn63Pb37) |
| Terminal form | BALL |
| Terminal pitch | 1 mm |
| Terminal location | BOTTOM |
| Maximum time at peak reflow temperature | 30 |
| width | 17 mm |
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