EE PLD, 45ns, PAL-Type, CMOS, PDIP24, 0.300 INCH, SLIM, PLASTIC, DIP-24
Parameter Name | Attribute value |
Is it Rohs certified? | incompatible |
Maker | AMD |
Parts packaging code | DIP |
package instruction | DIP, DIP24,.3 |
Contacts | 24 |
Reach Compliance Code | unknown |
Architecture | PAL-TYPE |
maximum clock frequency | 15 MHz |
JESD-30 code | R-PDIP-T24 |
JESD-609 code | e0 |
Dedicated input times | 3 |
Number of I/O lines | 16 |
Number of entries | 21 |
Output times | 16 |
Number of product terms | 188 |
Number of terminals | 24 |
Maximum operating temperature | 70 °C |
Minimum operating temperature | |
organize | 3 DEDICATED INPUTS, 16 I/O |
Output function | MACROCELL |
Package body material | PLASTIC/EPOXY |
encapsulated code | DIP |
Encapsulate equivalent code | DIP24,.3 |
Package shape | RECTANGULAR |
Package form | IN-LINE |
Peak Reflow Temperature (Celsius) | NOT SPECIFIED |
power supply | 5 V |
Programmable logic type | EE PLD |
propagation delay | 45 ns |
Certification status | Not Qualified |
Maximum supply voltage | 5.25 V |
Minimum supply voltage | 4.75 V |
Nominal supply voltage | 5 V |
surface mount | NO |
technology | CMOS |
Temperature level | COMMERCIAL |
Terminal surface | Tin/Lead (Sn/Pb) |
Terminal form | THROUGH-HOLE |
Terminal pitch | 2.54 mm |
Terminal location | DUAL |
Maximum time at peak reflow temperature | NOT SPECIFIED |