Am29DL162D/163D/164D
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
s
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between read and write operations
s
Multiple bank architectures
— Three devices available with different bank sizes (refer
to Table 2)
s
SecSi™ (Secured Silicon) Sector: Extra 64 KByte
sector
—
Factory locked and identifiable:
16 bytes available for
secure, random factory Electronic Serial Number;
verifiable as factory locked through autoselect
function. ExpressFlash option allows entire sector to
be available for factory-secured data
—
Customer lockable:
Can be read, programmed, or
erased just like other sectors. Once locked, data
cannot be changed
s
Zero Power Operation
— Sophisticated power management circuits reduce
power consumed during inactive periods to nearly
zero
s
Package options
— 48-ball FBGA
— 48-pin TSOP
s
Top or bottom boot block
s
Manufactured on 0.23 µm process technology
— Compatible with Am29DL16xC devices
s
Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash standard
PERFORMANCE CHARACTERISTICS
s
High performance
— Access time as fast 70 ns
— Program time: 7 µs/word typical utilizing Accelerate function
s
Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
s
Minimum 1 million write cycles guaranteed per sector
s
20 Year data retention at 125°C
— Reliable operation for the life of the system
SOFTWARE FEATURES
s
Data Management Software (DMS)
— AMD-supplied software manages data programming
and erasing, enabling EEPROM emulation
— Eases sector erase limitations
s
Supports Common Flash Memory Interface (CFI)
s
Erase Suspend/Erase Resume
— Suspends erase operations to allow programming in
same bank
s
Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
s
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
s
Any combination of sectors can be erased
s
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase
cycle completion
s
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state
machine to reading array data
s
WP#/ACC input pin
— Write protect (WP#) function allows protection of two
outermost boot sectors, regardless of sector protect status
— Acceleration (ACC) function accelerates program
timing
s
Sector protection
— Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within that
sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
21533
Rev:
D
Amendment/+3
Issue Date:
November 22, 2000
Refer to AMD’s Website (www.amd.com) for the latest information.
GENERAL DESCRIPTION
The Am29DL162D/163D/164D devices consists of 16
megabit, 3.0 volt-only flash memory devices, organized
as 1,048,576 words of 16 bits each or 2,097,152 bytes
o f 8 b i t s e a c h . Wo r d m o d e d a t a a p p e a r s o n
DQ0–DQ15; byte mode data appears on DQ0–DQ7.
The device is designed to be programmed in-system
with the standard 3.0 volt V
CC
supply, and can also be
programmed in standard EPROM programmers.
The device is available with an access time of 70, 90,
or 120 ns. The devices are offered in 48-pin TSOP and
48-ball FBGA packages. Standard control pins—chip
enable (CE#), write enable (WE#), and output enable
(OE#)—control normal read and write operations, and
avoid bus contention issues.
The device requires only a
single 3.0 volt power sup-
ply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
other flash sector, or may permanently lock their own
code there.
DMS (Data Management Software)
allows systems
to easily take advantage of the advanced architecture
of the simultaneous read/write product line by allowing
removal of EEPROM devices. DMS will also allow the
system software to be simplified, as it will perform all
functions necessary to modify data in file structures,
as opposed to single-byte modifications. To write or
update a particular piece of data (a phone number or
configuration data, for example), the user only needs
to state which piece of data is to be updated, and
where the updated data is located in the system. This
i s a n a d va n t a g e c o m p a r e d t o s y s te m s w h e r e
user-written software must keep track of the old data
location, status, logical to physical translation of the
data onto the Flash memory device (or memory de-
vices), and more. Using DMS, user-written software
does not need to interface with the Flash memory di-
rectly. Instead, the user's software accesses the Flash
memory by calling one of only six functions. AMD pro-
vides this software to simplify system design and
software integration efforts.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard.
Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device
sta-
tus bits:
RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to reading array data.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
o r y. T h i s c a n b e a c h i ev e d i n - s y s t e m o r v i a
programming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consumption is greatly re-
duced in both modes.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory
space into two banks. The device can improve overall
system performance by allowing a host system to pro-
gram or erase in one bank, then immediately and
simultaneously read from the other bank, with zero la-
tency. This releases the system from waiting for the
completion of program or erase operations.
The Am29DL162D/163D/164D devices uses multiple
bank architectures to provide flexibility for different ap-
plications. Three devices are available with the
following bank sizes:
Device
DL162
DL163
DL164
Bank 1
2 Mb
4 Mb
8 Mb
Bank 2
14 Mb
12 Mb
8 Mb
Am29DL162D/163D/164D Features
The
SecSi™
(Secured Silicon) Sector is an extra 64
Kbit sector capable of being permanently locked by
AMD or customers. The
SecSi Sector Indicator Bit
(DQ7) is permanently set to a 1 if the part is
factory
locked,
and set to a 0 if
customer lockable.
This way,
customer lockable parts can never be used to replace
a factory locked part.
Factory locked parts provide several options. The
SecSi Sector may store a secure, random 16 byte
ESN (Electronic Serial Number), customer code (pro-
grammed through AMD’s ExpressFlash service), or
both. Customer Lockable parts may utilize the SecSi
Sector as bonus space, reading and writing like any
2
Am29DL162D/163D/164D
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 6
Special Handling Instructions for FBGA Package .......................... 7
Chip Erase Command Sequence ................................................. 25
Sector Erase Command Sequence .............................................. 25
Erase Suspend/Erase Resume Commands ................................ 26
Figure 4. Erase Operation .................................................................... 26
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Table 1. Am29DL162D/163D/164D Device Bus Operations .................10
Command Definitions ................................................................... 27
Table 14. Am29DL162D/163D/164D Command Definitions ................. 27
Write Operation Status . . . . . . . . . . . . . . . . . . . . 28
DQ7: Data# Polling ...................................................................... 28
Figure 5. Data# Polling Algorithm ......................................................... 28
Word/Byte Configuration .............................................................. 10
Requirements for Reading Array Data .........................................10
Writing Commands/Command Sequences .................................. 11
Accelerated Program Operation ...............................................11
Autoselect Functions .................................................................11
Simultaneous Read/Write Operations with Zero Latency ............11
Standby Mode .............................................................................. 11
Automatic Sleep Mode .................................................................11
RESET#: Hardware Reset Pin .....................................................12
Output Disable Mode ...................................................................12
Table 2. Am29DL162D/163D/164D Device Bank Divisions ..................12
Table 3. Sector Addresses for Top Boot Sector Devices ......................13
Table 4. SecSi™ Sector Addresses for Top Boot Devices .................. 13
Table 5. Sector Addresses for Bottom Boot Sector Devices .................14
Table 6. SecSi™ Addresses for Bottom Boot Devices ........................ 14
RY/BY#: Ready/Busy# ................................................................. 29
DQ6: Toggle Bit I .......................................................................... 29
Figure 6. Toggle Bit Algorithm .............................................................. 29
DQ2: Toggle Bit II ......................................................................... 30
Reading Toggle Bits DQ6/DQ2 .................................................... 30
DQ5: Exceeded Timing Limits ...................................................... 30
DQ3: Sector Erase Timer ............................................................. 30
Table 15. Write Operation Status ......................................................... 31
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 32
Figure 7. Maximum Negative Overshoot Waveform ............................. 32
Figure 8. Maximum Positive Overshoot Waveform ............................. 32
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 32
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 9. I
CC1
Current vs. Time (Showing Active and Automatic
Sleep Currents)..................................................................................... 34
Figure 10. Typical I
CC1
vs. Frequency................................................... 34
Autoselect Mode .......................................................................... 15
Table 7. Am29DL162D/163D/164D Autoselect Codes, (High
Voltage Method) ...................................................................................15
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 11. Test Setup .......................................................................... 35
Table 16. Test Specifications ................................................................ 35
Sector/Sector Block Protection and Unprotection ........................ 16
Table 8. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection ...................................................................16
Table 9. Bottom Boot Sector/Sector Block Addresses
for Protection/Unprotection ...................................................................16
Key To Switching Waveforms ...................................................... 35
Figure 12. Input Waveforms and Measurement Levels ........................ 35
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36
Read-Only Operations ........................................................... 36
Figure 13. Read Operation Timings...................................................... 36
Write Protect (WP#) .....................................................................17
Temporary Sector/Sector Block Unprotect ...................................17
Figure 1. Temporary Sector Unprotect Operation ................................. 17
Figure 2. In-System Sector/Sector Block Protection and
Unprotection Algorithms........................................................................ 18
Hardware Reset (RESET#) .................................................... 37
Figure 14. Reset Timings...................................................................... 37
Word/Byte Configuration (BYTE#) ............................................... 38
Figure 15. BYTE# Timings for Read Operations .................................. 38
Figure 16. BYTE# Timings for Write Operations .................................. 38
SecSi™ (Secured Silicon) Sector Flash Memory Region ............19
Factory Locked: SecSi Sector Programmed and Protected At the
Factory ......................................................................................19
Customer Lockable: SecSi Sector NOT Programmed or
Protected At the Factory ...........................................................19
Hardware Data Protection ............................................................ 19
Low VCC Write Inhibit ...............................................................19
Write Pulse “Glitch” Protection .................................................. 20
Logical Inhibit ............................................................................20
Power-Up Write Inhibit .............................................................. 20
Erase and Program Operations ................................................... 39
Figure 17. Program Operation Timings ................................................
Figure 18. Accelerated Program Timing Diagram ................................
Figure 19. Chip/Sector Erase Operation Timings .................................
Figure 20. Back-to-back Read/Write Cycle Timings .............................
Figure 21. Data# Polling Timings (During Embedded Algorithms) .......
Figure 22. Toggle Bit Timings (During Embedded Algorithms) ............
Figure 23. DQ2 vs. DQ6 .......................................................................
40
40
41
42
42
43
43
Temporary Sector/Sector Block Unprotect ................................... 44
Figure 24. Temporary Sector/Sector Block Unprotect Timing Diagram 44
Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram 45
Common Flash Memory Interface (CFI) . . . . . . . 20
Table 10. CFI Query Identification String ..............................................
Table 11. System Interface String.........................................................
Table 12. Device Geometry Definition ..................................................
Table 13. Primary Vendor-Specific Extended Query ............................
20
21
21
22
Alternate CE# Controlled Erase and Program Operations ........... 46
Figure 26. Alternate CE# Controlled Write (Erase/Program)
Operation Timings ................................................................................ 47
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 23
Reading Array Data ...................................................................... 23
Reset Command .......................................................................... 23
Autoselect Command Sequence .................................................. 23
Enter SecSi™ Sector/Exit SecSi Sector Command Sequence ....24
Byte/Word Program Command Sequence ...................................24
Unlock Bypass Command Sequence .......................................24
Figure 3. Program Operation ................................................................ 25
Erase And Programming Performance . . . . . . .
Latchup Characteristics . . . . . . . . . . . . . . . . . . . .
TSOP And SO Pin Capacitance . . . . . . . . . . . . . .
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
48
48
48
FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
8 x 9 mm package ........................................................................ 49
TS 048—48-Pin Standard TSOP ................................................. 50
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 51
Revision A (September 1998) ...................................................... 51
Am29DL162D/163D/164D
3
Revision B (October 1998) ...........................................................51
Revision B+1 (October 1998) .......................................................51
Revision C (January 1998) ...........................................................51
Revision C+1 (March 19, 1999) ...................................................51
Revision C+2 (June 14, 1999) ...................................................... 51
Revision C+3 (August 9, 1999) .................................................... 51
Revision C+4 (August 23, 1999) .................................................. 51
Revision C+5 (October 18, 1999) ................................................ 51
Revision D (February 22, 2000) ................................................... 52
Revision D+1 (June 21, 2000) ..................................................... 52
Revision D+2 (September 4, 2000) .............................................. 52
Revision D+3 (November 22, 2000) ............................................. 52
4
Am29DL162D/163D/164D
PRODUCT SELECTOR GUIDE
Part Number
Speed Option
Max Access Time (ns)
CE# Access (ns)
OE# Access (ns)
Standard Voltage Range: V
CC
= 2.7–3.6 V
Am29DL162D/163D/164D
70
70
70
30
90
90
90
40
120
120
120
50
BLOCK DIAGRAM
V
CC
V
SS
OE# BYTE#
Y-Decoder
A0–A19
Upper Bank Address
Upper Bank
Latches and Control Logic
RY/BY#
A0–A19
RESET#
WE#
CE#
BYTE#
WP#/ACC
DQ0–DQ15
A0–A19
STATE
CONTROL
&
COMMAND
REGISTER
X-Decoder
Status
DQ0–DQ15
Control
DQ0–DQ15
X-Decoder
Lower Bank
A0–A19
Lower Bank Address
OE# BYTE#
Am29DL162D/163D/164D
Latches and
Control Logic
Y-Decoder
DQ0–DQ15
A0–A19
5
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