M28F256
256 Kbit (32Kb x8, Bulk) Flash Memory
5V
±
10% SUPPLY VOLTAGE
12V PROGRAMMING VOLTAGE
FAST ACCESS TIME: 90ns
BYTE PROGRAMMING TIME: 10µs typical
ELECTRICAL CHIP ERASE IN 1s RANGE
LOW POWER CONSUMPTION
– Standby Current: 5µA typical
10,000 ERASE/PROGRAM CYCLES
INTEGRATED ERASE/PROGRAM STOP
TIMER
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: A8h
32
1
PDIP32 (B)
PLCC32 (C)
Figure 1. Logic Diagram
DESCRIPTION
The M28F256 Flash memory is a non-volatile
memory that may be erased electrically at the chip
level and programmed by byte. It is organised as
32 Kbytes of 8 bits. It uses a command register
architectureto select the operatingmodes and thus
provides a simple microprocessor interface. The
device is offered in PDIP32 and PLCC32 pack-
ages.
A0-A14
VCC
VPP
15
8
DQ0-DQ7
W
Table 1. Signal Names
A0-A14
DQ0-DQ7
E
G
W
V
PP
V
CC
V
SS
Address Inputs
Data Inputs / Outputs
Chip Enable
Output Enable
Write Enable
Program Supply
Supply Voltage
Ground
M28F256
E
G
VSS
AI00688B
August 1998
1/20
M28F256
Figure 2A. DIP Pin Connections
VPP
NC
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
25
M28F256
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
AI00689
Figure 2B. LCC Pin Connections
VCC
W
NC
A14
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
A12
NC
NC
VPP
VCC
W
NC
1 32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A14
A13
A8
A9
A11
G
A10
E
DQ7
9
M28F256
25
17
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
AI00690
Warning:
NC = Not Connected
Warning:
NC = Not Connected
Table 2. Absolute Maximum Ratings
Symbol
T
A
T
BIAS
T
STG
V
IO (2, 3)
V
CC
Parameter
Ambient Operating Temperature
(4)
Temperature Under Bias
Storage Temperature
Input or Output Voltages
Supply Voltage
A9, RP Voltage
Program Supply Voltage, during Erase
or Programming
Value
–40 to 125
–50 to 125
–65 to 150
–0.6 to V
CC
+ 0.5
–0.6 to 7
–0.6 to 13.5
–0.6 to 14
Unit
°
C
°C
°
C
V
V
V
V
V
(A9, RP) (2)
V
PP
(2)
Notes:
1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
3. Maximum Voltage may overshoot to 7V during transition and for less than 20ns.
4. Depends on range.
DEVICE OPERATION
The M28F256 Flash memory employs a technol-
ogy similar to a 256K EPROM but adds to the
device functionality by providing electrical erasure
and programming. These functions are managed
by a command register. The functions that are
addressed via the command register depend on
the voltage applied to the V
PP
, program voltage,
input. When V
PP
is less than or equal to 6.5V, the
command register is disabled and M28F256 func-
tions as a read only memory providing operating
modes similar to an EPROM (Read, Output Dis-
able, Electronic Signature Read and Standby).
When V
PP
is raised to 12V the command register
is enabled and this provides, in addition, Erase and
Program operations.
2/20
M28F256
Table 3. Operations
V
PP
Read Only
V
PPL
(1)
Operation
Read
Output Disable
Standby
Electronic Signature
E
V
IL
V
IL
V
IH
V
IL
V
IL
V
IL
V
IL
V
IH
G
V
IL
V
IH
X
V
IL
V
IL
V
IH
V
IH
X
W
V
IH
V
IH
X
V
IH
V
IH
V
IL
Pulse
V
IH
X
A9
A9
X
X
V
ID
A9
A9
X
X
DQ0 - DQ7
Data Output
Hi-Z
Hi-Z
Codes
Data Output
Data Input
Hi-Z
Hi-Z
Read/Write
(2)
V
PPH
Read
Write
Output Disable
Standby
Notes:
1. X = V
IL
or V
IH
2. Refer also to the Command Table
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
V
IL
V
IH
DQ7
0
1
DQ6
0
0
DQ5
1
1
DQ4
0
0
DQ3
0
1
DQ2
0
0
DQ1
0
0
DQ0
0
0
Hex Data
20h
0A8h
READ ONLY MODES, V
PP
≤
6.5V
For all Read Only Modes, except Standby Mode,
the Write Enable input W should be High. In the
Standby Mode this input is ’don’t care’.
Read Mode.
The M28F256 has two enable inputs,
E and G, both of which must be Low in order to
output data from the memory. The Chip Enable (E)
is the power control and should be used for device
selection. Output Enable (G) is the output control
and should be used to gate data on to the output,
independant of the device selection.
Standby Mode.
In the Standby Mode the maxi-
mum supply current is reduced to 100µA. The
device is placed in the Standby Mode by applying
a High to the Chip Enable (E) input. When in the
StandbyMode the outputs are in a high impedance
state, independant of the Output Enable (G) input.
Output Disable Mode.
When the Output Enable
(G) is High the outputs are in a high impedance
state.
ElectronicSignature Mode.
This mode allows the
read out of two binary codes from the device which
identify the manufacturer and device type. This
mode is intended for use by programming equip-
ment to automatically select the correct erase and
programming algorithms. The Electronic Signature
Mode is active when a high voltage (11.5V to 13V)
is applied to addressline A9 with E and G Low. With
A0 Low the output data is the manufacturer code,
when A0 is High the output is the device type code.
All other address lines should be maintained Low
while reading the codes. The electronic signature
may also be accessed in Read/Write modes.
READ/WRITE MODES, 11.4V
≤
V
PP
≤
12.6V
When V
PP
is High both read and write operations
may be performed. These are defined by the con-
tents of an internal command register. Commands
may be written to this register to set-up and exe-
cute, Erase, Erase Verify, Program, ProgramVerify
and Reset modes. Each of these modes needs 2
cycles. Every mode starts with a write operation to
set-up the command,this is followed by either read
or write operations. The device expects the first
cycle to be a write operation and does not corrupt
data at any location in memory. Read mode is
set-up with one cycle only and may be followed by
any number of read operations to output data.
Electronic Signature Read mode is set-up with one
cycle and followed by a read cycle to output the
manufacturer or device codes.
3/20
M28F256
Table 5. Commands
(1)
Command
Read
Electronic
Signature
Setup Erase/
Erase
Erase Verify
Setup Program/
Program
Program Verify
Reset
Note:
1. X = V
IL
or V
IH
Cycles
Operation
1
2
Write
Write
Write
1st Cycle
A0-A14
X
X
X
DQ0-DQ7
00h
90h
20h
Write
Read
Read
Operation
2nd Cycle
A0-A14
DQ0-DQ7
0000h
0001h
20h
0A8h
2
2
2
2
2
X
X
20h
Data Output
Write
Write
A0-A14
X
0A0h
40h
Read
Write
Write
Write
X
X
0C0h
0FFh
Read
Write
A0-A14
X
X
Data Input
Data Output
0FFh
READ/WRITE MODES
(cont’d)
Awrite to the command register is made bybringing
W Low while E is Low. The falling edge of W latches
Addresses, while the rising edge latches Data,
which are used for those commands that require
address inputs, command input or provide data
output.
The supply voltage V
CC
and the program voltage
V
PP
can be applied in any order. When the device
is powered up or when V
PP
is
≤
6.5V the contents
of the command register default to 00h, thus auto-
matically setting-up Read operations. In addition a
specific command may be used to set the com-
mand register to 00h for reading the memory.
The system designer may choose to provide a
constant high V
PP
and use the register commands
for all operations, or to switch the V
PP
from low to
high only when needing to erase or program the
memory. All command register access is inhibited
when V
CC
falls belowthe Erase/Write Lockout Volt-
age (V
LKO
) at 2.5V.
If the device is deselected during Erasure, Pro-
gramming or Verification it will draw active supply
currents until the operations are terminated.
The device is protected against stress caused by
long erase or program times. If the end of Erase or
Programming operations are not terminated by a
Verify cycle within a maximum time permitted, an
internal stop timer automatically stops the opera-
tion. The device remains in an inactive state, ready
to start a Verify or Reset Mode operation.
Read Mode.
The Read Mode is the default at
power up or may be set-up by writing 00h to the
command register. Subsequent read operations
outputdata from the memory. Thememory remains
in the Read Mode until a new command is written
to the command register.
Electronic Signature Mode.
In order to select the
correct erase and programming algorithms for on-
board programming, the manufacturerand devices
code may be read directly. It is not neccessary to
apply a high voltage to A9 when using the com-
mand register. The Electronic Signature Mode is
set-up by writing 90h to the command register. The
following read cycle, with address inputs 0000h or
0001h, output the manufacturer or device type
codes. The command is terminated by writing an-
other valid command to the command register (for
example Reset).
4/20
M28F256
Table 6. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
≤
10ns
0.45V to 2.4V
0.8V to 2V
Figure 4. AC Testing Load Circuit
1.3V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
1N914
3.3kΩ
Figure 3. AC Testing Input Output Waveforms
2.4V
DEVICE
UNDER
TEST
CL = 100pF
OUT
2.0V
0.8V
CL includes JIG capacitance
AI00827
0.45V
AI00828
Table 7. Capacitance
(1)
(T
A
= 25
°C,
f = 1 MHz )
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
V
IN
= 0V
V
OUT
= 0V
Min
Max
6
12
Unit
pF
pF
Note:
1. Sampled only, not 100% tested
Erase and Erase Verify Modes.
The memory is
erased by first Programming all bytes to 00h, the
Erase command then erases them to 0FFh. The
Erase Verify command is then used to read the
memory byte-by-byte for a content of 0FFh.
The Erase Mode is set-up by writing 20h to the
command register. The write cycle is thenrepeated
to start the erase operation. Erasure starts on the
rising edge of W during this second cycle. Erase is
followed by an Erase Verify which reads an ad-
dressed byte.
Erase Verify Mode is set-up by writing 0A0h to the
command register and at the same time supplying
the address of the byte to be verified. The rising
edge of W during the set-up of the first Erase Verify
Mode stops the Erase operation. The following
read cycle is made with an internally generated
margin voltage applied; reading 0FFh indicates
that all bits of the addressed byte are fully erased.
The whole contents of the memory are verified by
repeating the Erase Verify Operation, first writing
the set-up code 0A0h with the address of the byte
to be verified and then reading the byte contentsin
a second read cycle.
As the Erase algorithm flow chart shows, when the
data read during Erase Verify is not 0FFh, another
Erase operation is performed and verification con-
tinues from the addressof the last verifiedbyte. The
command is terminated by writing another valid
command to the command register (for example
Program or Reset).
5/20
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