24AA52/24LCS52
2K 2.2V I
2
C
™
Serial EEPROM with Software Write-Protect
Features:
• Single supply with operation down to 1.8V
• Low-power CMOS technology:
- 1 mA active current, typical
- 1
μA
standby current, typical (I-temp)
• Organized as 1 block of 256 bytes (256 x 8)
• Software write protection for lower 128 bytes
• Hardware write protection for entire array
• 2-wire serial interface bus, I
2
C™ compatible
• Schmitt Trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz (24AA52) and 400 kHz (24LCS52)
compatibility
• Self-timed write cycle (including auto-erase)
• Page write buffer for up to 16 bytes
• ESD protection > 4,000V
• 1,000,000 erase/write cycles
• Data retention > 200 years
• 8-lead PDIP, SOIC, TSSOP, MSOP and DFN
packages
• Pb-free finishes available
• Available for extended temperature ranges:
- Industrial (I): -40°C to +85°C
Description:
The Microchip Technology Inc. 24AA52/24LCS52
(24XXX52*) is a 2 Kbit Electrically Erasable PROM
capable of operation across a broad voltage range
(1.8V to 5.5V). This device has a software write-protect
feature for the lower half of the array, as well as an
external pin that can be used to write-protect the entire
array. The software write-protect feature is enabled by
sending the device a special command. Once this
feature has been enabled, it cannot be reversed. In
addition to the software protect feature, there is a WP
pin that can be used to write-protect the entire array,
regardless of whether the software write-protect
register has been written or not. This allows the system
designer to protect none, half, or all of the array,
depending on the application. The device is organized
as one block of 256 x 8-bit memory with a 2-wire serial
interface. Low-voltage design permits operation down
to 1.8V, with standby and active currents of only 1
μA
and 1 mA, respectively. The 24XXX52 also has a page
write capability for up to 16 bytes of data. The 24XXX52
is available in the standard 8-pin PDIP, surface mount
SOIC, TSSOP, MSOP and DFN packages.
Block Diagram
A0 A1 A2
WP
HV Generator
Software write
protected area
(00h-7Fh)
Standard
Array
SDA SCL
V
CC
V
SS
Write-Protect
Circuitry
YDEC
Sense Amp.
R/W Control
Device Selection Table
Part
Number
24AA52
24LCS52
Note 1:
V
CC
Range
1.8-5.5
2.2-5.5
Max Clock
Frequency
400 kHz
(1)
400 kHz
Temp
Ranges
I
I
I/O
Control
Logic
Memory
Control
Logic
XDEC
100 kHz for V
CC
<2.2V
Package Types
PDIP/SOIC/TSSOP/MSOP/DFN
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
A0 1
A1 2
A2 3
V
SS
4
8 V
CC
7 WP
6 SCL
5 SDA
*24XXX52 is used in this document as a generic part number
for the 24AA52/24LCS52 devices.
©
2005 Microchip Technology Inc.
DS21166J-page 1
24AA52/24LCS52
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.3V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins
......................................................................................................................................................≥
4 kV
† NOTICE:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC SPECIFICATIONS
V
CC
= +1.8V to +5.5V
Industrial (I): T
A
= -40°C to +85°C
Min
—
0.7 V
CC
—
0.05 V
CC
—
—
—
—
—
—
Standby current
—
—
Typ
—
—
—
—
—
—
—
—
1.0
0.20
0.36
—
Max
—
—
0.3 V
CC
—
0.40
±1
±1
10
3.0
1.0
1.0
—
Units
—
V
V
V
V
μA
μA
pF
mA
mA
μA
—
—
0.2 V
CC
for V
CC
< 2.5V
(Note)
I
OL
= 3.0 mA, V
CC
= 2.5V
V
IN
= V
SS
or V
CC
V
OUT
= V
SS
or V
CC
V
CC
= 5.0V
(Note)
T
A
= 25°C, F
CLK
= 1 MHz
V
CC
= 5.5V, SCL = 400 kHz
—
Industrial
SDA = SCL = V
CC
A0, A1, A2, WP = V
SS
Conditions
DC CHARACTERISTICS
Param.
Symbol
No.
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
V
IH
—
V
IL
V
HYS
V
OL
I
LI
I
LO
C
IN
,
C
OUT
I
CC
read
I
CCS
Characteristic
A0, A1, A2, SCL, SDA
and WP pins
High-level input voltage
Low-level input voltage
Hysteresis of Schmitt
Trigger inputs
Low-level output voltage
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
I
CC
write Operating current
Note:
This parameter is periodically sampled and not 100% tested.
DS21166J-page 2
©
2005 Microchip Technology Inc.
24AA52/24LCS52
TABLE 1-2:
AC SPECIFICATIONS
V
CC
= +1.8V to +5.5V
Industrial (I): T
A
= -40°C to +85°C
Min
—
—
600
4000
1300
4700
—
—
—
600
4000
600
4700
0
100
250
600
4000
—
—
1300
4700
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
400
100
—
—
—
—
300
1000
300
—
—
—
—
—
—
—
—
—
900
3500
—
—
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
2.2V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
<
2.5V (24AA52)
2.2V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
<
2.5V (24AA52)
2.2V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
<
2.5V (24AA52)
2.2V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
<
2.5V (24AA52)
(Note 1)
2.2V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
<
2.5V (24AA52)
2.2V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
<
2.5V (24AA52)
(Note 2)
2.2V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
<
2.5V (24AA52)
2.2V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
<
2.5V (24AA52)
2.2V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
<
2.5V (24AA52)
2.2V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
<
2.5V (24AA52)
AC CHARACTERISTICS
Param.
Symbol
No.
1
2
3
4
5
6
7
8
9
10
11
12
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
Characteristic
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
(Note 1)
SDA and SCL fall time
Start condition hold time
Start condition setup
time
Data input hold time
Data input setup time
Stop condition setup
time
Output valid from clock
(Note 2)
Bus free time: Time the
bus must be free before
a new transmission can
start
13
T
OF
Output fall time from V
IH
20 + 0.1 C
B
minimum to V
IL
—
maximum
Input filter spike
suppression
(SDA and SCL pins)
Write cycle time
(byte or page)
Endurance
—
—
—
—
250
250
50
ns
2.2V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
<
2.5V (24AA52)
(Note 1 and Note 3)
14
T
SP
ns
15
16
T
WC
—
—
1M
—
—
5
—
ms
—
cycles 25°C, V
CC
= 5.0V, Block
mode
(Note 4)
Note 1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3:
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a T
I
specification for standard operation.
4:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.microchip.com.
©
2005 Microchip Technology Inc.
DS21166J-page 3
24AA52/24LCS52
FIGURE 1-1:
BUS TIMING DATA
5
3
4
2
SCL
7
8
6
14
11
12
9
10
SDA
IN
SDA
OUT
FIGURE 1-2:
BUS TIMING START/STOP
D4
SCL
7
6
10
SDA
Start
Stop
DS21166J-page 4
©
2005 Microchip Technology Inc.
24AA52/24LCS52
2.0
FUNCTIONAL DESCRIPTION
3.4
Data Valid (D)
The 24XXX52 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data, as a receiver. The bus has to be
controlled by a master device, which generates the
Serial Clock (SCL), controls the bus access and gener-
ates the Start and Stop conditions, while the 24XXX52
works as slave. Both master and slave can operate as
transmitter or receiver, but the master device
determines which mode is activated.
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited; although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first-in,
first-out (FIFO) fashion.
3.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse, which is associated with this Acknowledge bit.
Note:
The 24XXX52 does not generate any
Acknowledge
bits
if
an
internal
programming cycle is in progress.
3.1
Bus Not Busy (A)
Both data and clock lines remain high.
3.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end-of-
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XXX52) will leave the data
line high to enable the master to generate the Stop
condition.
FIGURE 3-1:
(A)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B)
(D)
(D)
(C)
(A)
SCL
SDA
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
©
2005 Microchip Technology Inc.
DS21166J-page 5
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