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Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> ICS9250YF-30-T
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ICS9250YF-30-T

Description
Processor Specific Clock Generator, 200MHz, PDSO56, 0.300 INCH, SSOP-56
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size338KB，15 Pages
ManufacturerIDT (Integrated Device Technology)
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ICS9250YF-30-T Overview

Processor Specific Clock Generator, 200MHz, PDSO56, 0.300 INCH, SSOP-56

ICS9250YF-30-T Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeSSOP
package instructionSSOP,
Contacts56
Reach Compliance Codecompliant
ECCN codeEAR99
JESD-30 codeR-PDSO-G56
JESD-609 codee0
length18.415 mm
Number of terminals56
Maximum operating temperature70 °C
Minimum operating temperature
Maximum output clock frequency200 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)225
Master clock/crystal nominal frequency14.318 MHz
Certification statusNot Qualified
Maximum seat height2.794 mm
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width7.5 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, PROCESSOR SPECIFIC

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Download Datasheet
Integrated
Circuit
Systems, Inc.
ICS9250-30
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
810/810E and Solano type chipset
Output Features:
•
2 - CPUs @ 2.5V, up to 200MHz.
•
13 - SDRAM @ 3.3V, up to 200MHz.
•
3 - 3V66 @ 3.3V, 2x PCI MHz.
•
8 - PCI @3.3V.
•
1 - 48MHz, @3.3V fixed.
•
1 - 24/48MHz @ 3.3V
•
1 - REF @3.3V, 14.318MHz.
•
1 - IOAPIC @ 2.5V.
Features:
•
Support PC133 SDRAM.
•
Up to 200MHz frequency support
•
Support power management through PD#.
•
Spread spectrum for EMI control
(± 0.25% Center Spread or 0 to -0.5% down spread)
•
Uses external 14.318MHz crystal
•
FS pins for frequency select
Key Specifications:
•
CPU Output Jitter: <250ps
•
CPU Output Skew: <175ps
•
PCI Output Skew: <500ps
•
3V66 Output Skew <175ps
•
For group skew timing, please refer to the
Group Timing Relationship Table.
Pin Configuration
VDDREF
X1
X2
GNDREF
GND3V66
3V66-0
3V66-1
3V66-2
VDD3V66
VDDPCI
1
*FS0/PCICLK0
1
*FS1/PCICLK1
1
*SEL24_48#/PCICLK2
GNDPCI
PCICLK3
PCICLK4
PCICLK5
VDDPCI
PCICLK6
PCICLK7
GNDPCI
PD#
SCLK
SDATA
VDDSDR
SDRAM11
SDRAM10
GNDSDR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF0/FS4*
VDDLAPIC
IOAPIC
VDDLCPU
CPUCLK0
CPUCLK1
GNDLCPU
GNDSDR
SDRAM0
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
SDRAM5
GNDSDR
SDRAM6
SDRAM7
SDRAM_F
VDDSDR
GND48
1
24_48MHz/FS2 *
1
48MHz/FS3*
VDD48
VDDSDR
SDRAM8
SDRAM9
GNDSDR
1
56-Pin 300 mil SSOP
1. These pins will have 1.5 to 2X drive strength.
* 120K ohm pull-up to VDD on indicated inputs.
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz
24_48MHz
Functionality
FS4 FS3 FS2 FS1 FS0 CPU SDRAM
0
0
0
0
0
66.67 100.00
0
0
0
1
1
68.33 102.50
0
0
1
1
0
80.00 120.00
0
0
1
1
1
83.00 124.50
0
1
0
0
0 100.00 100.00
0
1
0
1
1 103.00 103.00
0
1
1
1
0 115.00 115.00
0
1
1
1
1 200.00 200.00
1
0
0
0
0 133.33 133.33
1
0
0
0
1 166.67 166.67
1
0
0
1
1 137.00 137.00
1
0
1
1
1 160.00 160.00
1
1
0
0
0 133.33 100.00
1
1
0
0
1 166.67 125.00
1
1
0
1
1 137.00 102.75
1
1
1
1
1 160.00 120.00
3V66
66.67
68.33
80.00
83.00
66.67
68.67
76.67
66.67
66.67
83.34
68.50
80.00
66.67
83.34
68.50
80.00
PCI
33.33
34.17
40.00
41.50
33.33
34.33
38.33
33.33
33.33
41.67
34.25
40.00
33.33
41.67
34.25
40.00
REF0
CPU
DIVDER
2
CPUCLK [1:0]
SDRAM
DIVDER
12
SDRAM [11:0]
SDRAM_F
FS[4:0]
PD#
SEL24_48#
SDATA
SCLK
Control
Logic
Config.
Reg.
IOAPIC
DIVDER
IOAPIC
PCI
DIVDER
8
PCICLK [7:0]
3V66
DIVDER
3
3V66 [2:0]
For other hardware/I
2
C selectable frequencies please
refer to Byte 0 frequency select register.
0398A—07/03/02
ICS9250-30

ICS9250YF-30-T Related Products

ICS9250YF-30-T ICS9250YF-30LF-T
Description Processor Specific Clock Generator, 200MHz, PDSO56, 0.300 INCH, SSOP-56 Processor Specific Clock Generator, 200MHz, PDSO56, 0.300 INCH, SSOP-56
Is it lead-free? Contains lead Lead free
Is it Rohs certified? incompatible conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code SSOP SSOP
package instruction SSOP, SSOP,
Contacts 56 56
Reach Compliance Code compliant compliant
ECCN code EAR99 EAR99
JESD-30 code R-PDSO-G56 R-PDSO-G56
JESD-609 code e0 e3
length 18.415 mm 18.415 mm
Number of terminals 56 56
Maximum operating temperature 70 °C 70 °C
Maximum output clock frequency 200 MHz 200 MHz
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SSOP SSOP
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 225 260
Master clock/crystal nominal frequency 14.318 MHz 14.318 MHz
Certification status Not Qualified Not Qualified
Maximum seat height 2.794 mm 2.794 mm
Maximum supply voltage 3.465 V 3.465 V
Minimum supply voltage 3.135 V 3.135 V
Nominal supply voltage 3.3 V 3.3 V
surface mount YES YES
technology CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL
Terminal surface Tin/Lead (Sn/Pb) Matte Tin (Sn)
Terminal form GULL WING GULL WING
Terminal pitch 0.635 mm 0.635 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature 30 30
width 7.5 mm 7.5 mm
uPs/uCs/peripheral integrated circuit type CLOCK GENERATOR, PROCESSOR SPECIFIC CLOCK GENERATOR, PROCESSOR SPECIFIC

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