IDT72V291L20PF8 datasheet, PDF

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IDT72V291L20PF8: DescriptionFIFO, 128KX9, 12ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64; Categorystorage storage; File Size238KB，26 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT72V291L20PF8 Overview

FIFO, 128KX9, 12ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64

IDT72V291L20PF8 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	PLASTIC, TQFP-64
Contacts	64
Reach Compliance Code	not_compliant
ECCN code	EAR99
Maximum access time	12 ns
Maximum clock frequency (fCLK)	50 MHz
period time	20 ns
JESD-30 code	S-PQFP-G64
JESD-609 code	e0
length	14 mm
memory density	1179648 bit
Memory IC Type	OTHER FIFO
memory width	9
Humidity sensitivity level	3
Number of functions	1
Number of terminals	64
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX9
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP64,.66SQ,32
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.015 A
Maximum slew rate	0.055 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	14 mm

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3.3 VOLT CMOS SuperSync FIFO™

65,536 x 9

131,072 x 9

.EATURES:

•

IDT72V281

IDT72V291

•

Choose among the following memory organizations:

IDT72V281

65,536 x 9

IDT72V291

131,072 x 9

Pin-compatible with the IDT72V261/72V271 SuperSync FIFOs

10ns read/write cycle time (6.5ns access time)

Fixed, low first word data latency time

Auto power down minimizes standby power consumption

Master Reset clears entire FIFO

Partial Reset clears data, but retains programmable

settings

Retransmit operation with fixed, low first word data

latency time

Empty, Full and Half-Full flags signal FIFO status

Programmable Almost-Empty and Almost-Full flags, each flag can

default to one of two preselected offsets

Program partial flags by either serial or parallel means

Select IDT Standard timing (using

and

flags) or First Word

Fall Through timing (using

and

flags)

Output enable puts data outputs into high impedance state

Easily expandable in depth and width

Independent Read and Write clocks (permit reading and writing

simultaneously)

Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-pin

Slim Thin Quad Flat Pack (STQFP)

High-performance submicron CMOS technology

Industrial Temperature Range (-40°C to + 85°C) is available

DESCRIPTION:

The IDT72V281/72V291 are exceptionally deep, high speed, CMOS

First-In-First-Out (FIFO) memories with clocked read and write controls.

These FIFOs offer numerous improvements over previous SuperSync

FIFOs, including the following:

•

The limitation of the frequency of one clock input with respect to the other has

been removed. The Frequency Select pin (FS) has been removed, thus

it is no longer necessary to select which of the two clock inputs, RCLK or

WCLK, is running at the higher frequency.

•

The period required by the retransmit operation is now fixed and short.

•

The first word data latency period, from the time the first word is written to an

empty FIFO to the time it can be read, is now fixed and short. (The variable

clock cycle counting delay associated with the latency period found on

previous SuperSync devices has been eliminated on this SuperSync family.)

.UNCTIONAL BLOCK DIAGRAM

WEN

WCLK

-D

LD SEN

INPUT REGISTER

OFFSET REGISTER

FF/IR

PAF

EF/OR

PAE

FWFT/SI

WRITE CONTROL

LOGIC

RAM ARRAY

65,536 x 9

131,072 x 9

FLAG

LOGIC

WRITE POINTER

READ POINTER

OUTPUT REGISTER

MRS

PRS

READ

CONTROL

LOGIC

RESET

LOGIC

RCLK

REN

-Q

4513 drw 01

SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE



2001

Integrated Device Technology, Inc.

APRIL 2001

DSC-4513/1

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