1
®
XC9572 In-System Programmable
CPLD
1
1*
December 4, 1998 (Version 3.0)
Product Specification
Features
•
•
•
•
•
7.5 ns pin-to-pin logic delays on all pins
f
CNT
to 125 MHz
72 macrocells with 1,600 usable gates
Up to 72 user I/O pins
5 V in-system programmable (ISP)
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs
3.3 V or 5 V I/O capability
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP
and 100-pin TQFP packages
Power Management
Power dissipation can be reduced in the XC9572 by config-
uring macrocells to standard or low-power modes of opera-
tion. Unused macrocells are turned off to minimize power
dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
I
CC
(mA) =
MC
HP
(1.7) + MC
LP
(0.9) + MC (0.006 mA/MHz) f
Where:
MC
HP
= Macrocells in high-performance mode
MC
LP
= Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1
shows a typical calculation for the XC9572 device.
•
•
•
•
•
•
•
•
•
•
•
•
200
erform
High P
Typical I
cc
(ma)
a n ce
(160)
(125)
100
o we r
Low P
(100)
Description
The XC9572 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of four
36V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 7.5 ns. See
Figure 2
for the architec-
ture overview.
(65)
0
50
Clock Frequency (MHz)
100
Figure 1: Typical I
CC
vs. Frequency for XC9572
December 4, 1998 (Version 3.0)
1
XC9572 In-System Programmable CPLD
3
JTAG Port
1
JTAG
Controller
In-System Programming Controller
36
I/O
I/O
I/O
I/O
FastCONNECT Switch Matrix
36
18
18
Function
Block 1
Macrocells
1 to 18
Function
Block 2
Macrocells
1 to 18
I/O
Blocks
I/O
I/O
I/O
I/O
3
I/O/GCK
1
I/O/GSR
I/O/GTS
2
36
18
Function
Block 3
Macrocells
1 to 18
36
18
Function
Block 4
Macrocells
1 to 18
X5921
Figure 2: XC9572 Architecture
Note:
Function Block outputs (indicated by the bold line) drive the I/O Blocks directly
2
December 4, 1998 (Version 3.0)
XC9572 In-System Programmable CPLD
Absolute Maximum Ratings
Symbol
V
CC
V
IN
V
TS
T
STG
T
SOL
Parameter
Supply voltage relative to GND
DC input voltage relative to GND
Voltage applied to 3-state output with respect to GND
Storage temperature
Max soldering temperature (10 s @ 1/16 in = 1.5 mm)
Value
-0.5 to 7.0
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
-65 to +150
+260
Units
V
V
V
°C
°C
Warning:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
of time may affect device reliability.
Recommended Operation Conditions
Symbol
V
CCINT
V
CCIO
V
IL
V
IH
V
O
Parameter
1
Min
4.75
(4.5)
4.75 (4.5)
3.0
0
2.0
0
Max
5.25
(5.5)
5.25 (5.5)
3.6
0.80
V
CCINT
+0.5
V
CCIO
Units
V
V
V
V
V
V
Supply voltage for internal logic and input buffer
Supply voltage for output drivers for 5 V operation
Supply voltage for output drivers for 3.3 V operation
Low-level input voltage
High-level input voltage
Output voltage
Note:
1. Numbers in parenthesis are for industrial temperature range versions.
Endurance Characteristics
Symbol
t
DR
N
PE
Data Retention
Program/Erase Cycles
Parameter
Min
20
10,000
Max
-
-
Units
Years
Cycles
December 4, 1998 (Version 3.0)
3
XC9572 In-System Programmable CPLD
DC Characteristics Over Recommended Operating Conditions
Symbol
V
OH
Parameter
Output high voltage for 5 V operation
Output high voltage for 3.3 V operation
V
OL
Output low voltage for 5 V operation
Output low voltage for 3.3 V operation
I
IL
I
IH
C
IN
I
CC
Input leakage current
I/O high-Z leakage current
I/O capacitance
Operating Supply Current
(low power mode, active)
Test Conditions
I
OH
= -4.0 mA
V
CC
= Min
I
OH
= -3.2 mA
V
CC
= Min
I
OL
= 24 mA
V
CC
= Min
I
OL
= 10 mA
V
CC
= Min
V
CC
= Max
V
IN
= GND or V
CC
V
CC
= Max
V
IN
= GND or V
CC
V
IN
= GND
f = 1.0 MHz
V
I
= GND, No load
f = 1.0 MHz
Min
2.4
2.4
0.5
0.4
±10.0
±10.0
10.0
65 (Typ)
Max
Units
V
V
V
V
µA
µA
pF
ma
AC Characteristics
Symbol
t
PD
t
SU
t
H
t
CO
f
CNT
1
f
SYSTEM
2
t
PSU
t
PH
t
PCO
t
OE
t
OD
t
POE
t
POD
t
WLH
Parameter
I/O to output valid
I/O setup time before GCK
I/O hold time after GCK
GCK to output valid
16-bit counter frequency
Multiple FB internal operating frequency
I/O setup time before p-term clock input
I/O hold time after p-term clock input
P-term clock to output valid
GTS to output valid
GTS to output disable
Product term OE to output enabled
Product term OE to output disabled
GCK pulse width (High or Low)
XC9572-7
Min
4.5
0.0
4.5
125.0
83.3
0.5
4.0
8.5
5.5
5.5
9.5
9.5
4.0
4.5
111.1
66.7
2.0
4.0
10.0
6.0
6.0
10.0
10.0
5.5
Max
7.5
6.0
0.0
6.0
95.2
55.6
4.0
4.0
12.0
11.0
11.0
14.0
14.0
XC9572-10
Min
Max
10.0
8.0
0.0
8.0
XC9572-15
Min
Max
15.0
Units
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Note:
1. f
CNT
is the fastest 16-bit counter frequency available, using the local feedback when applicable.
f
CNT
is also the Export Control Maximum flip-flop toggle rate, f
TOG
.
2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.
V
TEST
R
1
Device Output
R
2
C
L
Output Type
V
CCIO
5.0 V
3.3 V
V
TEST
5.0 V
3.3 V
R
1
160
Ω
260
Ω
R
2
120
Ω
360
Ω
C
L
35 pF
35 pF
X5906
Figure 3: AC Load Circuit
4
December 4, 1998 (Version 3.0)
XC9572 In-System Programmable CPLD
Internal Timing Parameters
Symbol
Parameter
XC9572-7
Min
Max
2.5
1.5
4.5
5.5
2.5
0.0
3.0
2.0
4.5
0.5
1.5
3.0
0.5
6.5
7.5
2.0
10.0
8.0
4.0
1.0
4.0
10.0
2.5
11.0
9.5
3.5
1.0
4.5
2.5
3.5
0.5
7.0
10.0
3.0
11.5
11.0
3.5
1.0
5.0
XC9572-10
Min
Max
3.5
2.5
6.0
6.0
3.0
0.0
3.0
2.5
3.5
1.0
3.5
4.5
0.5
8.0
XC9572-15
Min
Max
4.5
3.0
7.5
11.0
4.5
0.0
2.5
3.0
5.0
3.0
Units
Buffer Delays
t
IN
Input buffer delay
t
GCK
GCK buffer delay
t
GSR
GSR buffer delay
t
GTS
GTS buffer delay
t
OUT
Output buffer delay
t
EN
Output buffer enable/disable delay
Product Term Control Delays
t
PTCK
Product term clock delay
t
PTSR
Product term set/reset delay
t
PTTS
Product term 3-state delay
Internal Register and Combinatorial delays
t
PDI
Combinatorial logic propagation delay
t
SUI
Register setup time
t
HI
Register hold time
t
COI
Register clock to output valid time
t
AOI
Register async. S/R to output delay
t
RAI
Register async. S/R recovery before clock
t
LOGI
Internal logic delay
t
LOGILP
Internal low power logic delay
Feedback Delays
t
F
FastCONNECT matrix feedback delay
t
LF
Function Block local feeback delay
Time Adders
t
PTA
3
Incremental Product Term Allocator delay
t
SLEW
Slew-rate limited delay
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
3. t
PTA
is multiplied by the span of the function as defined in the family data sheet.
December 4, 1998 (Version 3.0)
5
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