XCR3128-12TQ128I datasheet, PDF

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XCR3128-12TQ128I: DescriptionXCR3128: 128 Macrocell CPLD; CategoryProgrammable logic devices Programmable logic; File Size116KB，18 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

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XCR3128-12TQ128I Overview

XCR3128: 128 Macrocell CPLD

XCR3128-12TQ128I Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	XILINX
Parts packaging code	QFP
package instruction	LFQFP, QFP128,.63X.87,20
Contacts	128
Reach Compliance Code	unknow
Other features	YES
maximum clock frequency	69 MHz
In-system programmable	YES
JESD-30 code	R-PQFP-G128
JTAG BST	YES
length	20 mm
Dedicated input times	2
Number of I/O lines	96
Number of macro cells	128
Number of terminals	128
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2 DEDICATED INPUTS, 96 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP128,.63X.87,20
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE, FINE PITCH
power supply	3.3 V
Programmable logic type	EE PLD
propagation delay	12 ns
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	14 mm

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APPLICATION NOTE

XCR3128: 128 Macrocell CPLD

14*

DS034 (v1.2) August 10, 2000

Product Specification

Introduction

•

Industry's first TotalCMOS™ PLD - both CMOS design

and process technologies

Fast Zero Power (FZP™) design technique provides

ultra-low power and very high speed

IEEE 1149.1-compliant, JTAG Testing Capability

- Four pin JTAG interface (TCK, TMS, TDI, TDO)

- IEEE 1149.1 TAP Controller

- JTAG commands include: Bypass, Sample/Preload,

Extest, Usercode, Idcode, HighZ

3.3V, In-System Programmable (ISP) using the JTAG

interface

- On-chip supervoltage generation

- ISP commands include: Enable, Erase, Program,

Verify

- Supported by multiple ISP programming plat-

forms

High speed pin-to-pin delays of 10 ns

Ultra-low static power of less than 100

µA

100% routable with 100% utilization while all pins and

all macrocells are fixed

Deterministic timing model that is extremely simple to

use

Four clocks available

Programmable clock polarity at every macrocell

Support for asynchronous clocking

Innovative XPLA™ architecture combines high-speed

with extreme flexibility

1000 erase/program cycles guaranteed

20 years data retention guaranteed

Logic expandable to 37 product terms

PCI compliant

Advanced 0.5µ E

CMOS process

Security bit prevents unauthorized access

Design entry and verification using industry standard

and Xilinx CAE tools

Reprogrammable using industry standard device

programmers

Innovative control term structure provides either sum

terms or product terms in each logic block for:

- Programmable 3-state buffer

- Asynchronous macrocell register preset/reset

- Programmable global 3-state pin facilitates "bed of

nails" testing without using logic resources

- Available in PLCC, VQFP, and PQFP packages

- Available in both commercial and industrial grades

Description

The XCR3128 CPLD (Complex Programmable Logic

Device) is the third in a family of CoolRunner

CPLDs from

Xilinx. These devices combine high speed and zero power

in a 128 macrocell CPLD. With the FZP design technique,

the XCR3128 offers true pin-to-pin speeds of 10 ns, while

simultaneously delivering power that is less than 100

µA

standby without the need for ‘ turbo-bits’ or other

power-down schemes. By replacing conventional sense

amplifier methods for implementing product terms (a tech-

nique that has been used in PLDs since the bipolar era)

with a cascaded chain of pure CMOS gates, the dynamic

power is also substantially lower than any competing

CPLD. These devices are the first TotalCMOS PLDs, as

they use both a CMOS process technology

and

the pat-

ented full CMOS FZP design technique. For 5V applica-

tions, Xilinx also offers the high speed XCR5128 CPLD that

offers these features in a full 5V implementation.

The Xilinx FZP CPLDs utilize the patented XPLA

(eXtended Programmable Logic Array) architecture. The

XPLA architecture combines the best features of both PLA

and PAL type structures to deliver high speed and flexible

logic allocation that results in superior ability to make

design changes with fixed pinouts. The XPLA structure in

each logic block provides a fast 10 ns PAL path with five

dedicated product terms per output. This PAL path is joined

by an additional PLA structure that deploys a pool of 32

product terms to a fully programmable OR array that can

allocate the PLA product terms to any output in the logic

block. This combination allows logic to be allocated effi-

ciently throughout the logic block and supports as many as

37 product terms on an output. The speed with which logic

is allocated from the PLA array to an output is only 2.5 ns,

regardless of the number of PLA product terms used, which

results in worst case t

’s of only 12.5 ns from any pin to

any other pin. In addition, logic that is common to multiple

outputs can be placed on a single PLA product term and

shared across multiple outputs via the OR array, effectively

increasing design density.

The XCR3128 CPLDs are supported by industry standard

CAE tools (CadencE/OrCAD, Exemplar Logic, Mentor,

Synopsys, Synario, Viewlogic, and Synplicity), using text

(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-

ification uses industry standard simulators for functional

and timing simulation. Development is supported on per-

sonal computer, Sparc, and HP platforms. Device fitting

uses a Xilinx developed tool, XPLA Professional (available

on the Xilinx web site).

•

DS034 (v1.2) August 10, 2000

www.xilinx.com

1-800-255-7778

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