400MHz Low Voltage PECL Clock Synthesizer
MPC9229
DATA SHEET
The MPC9229 is a 3.3 V compatible, PLL based clock synthesizer targeted for high
performance clock generation in mid-range to high-performance telecom, networking and
computing applications. With output frequencies from 25 MHz to 400 MHz and the support of
differential PECL output signals the device meets the needs of the most demanding clock
applications.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
25 MHz to 400 MHz Synthesized Clock Output Signal
Differential PECL Output
LVCMOS Compatible Control Inputs
On-Chip Crystal Oscillator for Reference Frequency Generation
3.3-V Power Supply
Fully Integrated PLL
Minimal Frequency Overshoot
Serial 3-Wire Programming Interface
Parallel Programming Interface for Power-Up
32-Lead LQFP and 28-Lead PLCC Packaging
32-Lead and 28-Lead Pb-Free Package Available
SiGe Technology
Ambient Temperature Range 0°C to +70°C
Pin and Function Compatible to the MC12429
MPC9229
400 MHz LOW VOLTAGE
CLOCK SYNTHESIZER
FN SUFFIX
28-LEAD PLCC PACKAGE
CASE 776-02
EI SUFFIX
28-LEAD PLCC PACKAGE
Pb-FREE PACKAGE
CASE 776-02
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-04
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-04
Functional Description
The internal crystal oscillator uses the external quartz crystal as the basis of its frequency
reference. The frequency of the internal crystal oscillator is divided by 16 and then multiplied
by the PLL. The VCO within the PLL operates over a range of 800 to 1600 MHz. Its output is
ORDERING INFORMATION
scaled by a divider that is configured by either the serial or parallel interfaces. The crystal
Temp.
Case
oscillator frequency f
XTAL
, the PLL feedback-divider M and the PLL post-divider N determine
Device
Package
Range
No.
the output frequency.
The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be
MPC9229FN
0°C
776-02
PLCC
4⋅M times the reference frequency by adjusting the VCO control voltage. Note that for some
to +70°C
MPC9229EI
776-02
PLCC
values of M (either too high or too low) the PLL will not achieve phase lock. The PLL will be
stable if the VCO frequency is within the specified VCO frequency range (800 to 1600 MHz).
MPC9229FA
873A-03
LQFP
The M-value must be programmed by the serial or parallel interface.
MPC9229AC
873A-03
LQFP
The PLL post-divider N is configured through either the serial or the parallel interfaces, and
can provide one of four division ratios (1, 2, 4, or 8). This divider extends performance of the
part while providing a 50% duty cycle. The output driver is driven differentially from the output
divider, and is capable of driving a pair of transmission lines terminated 50
Ω
to V
CC
–
2.0 V. The positive supply voltage for the internal PLL
is separated from the power supply for the core logic and output drivers to minimize noise induced jitter.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs to configure
the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On the LOW-to-HIGH
transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are
provided on the M[8:0] and N[1:0] inputs prevent the LVCMOS compatible control inputs from floating.
The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial
input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will
capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. Refer to
Programming Interface
for more information.
The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. In order to minimize the
PLL jitter, it is recommended to avoid active signal on the TEST output.
MPC9229 REVISION 3 AUGUST 6, 2009
1
©2009 Integrated Device Technology, Inc.
MPC9229 Data Sheet
400MHZ LOW VOLTAGE PECL CLOCK SYNTHESIZER
XTAL_IN
XTAL_OUT
XTAL
10 – 20 MHz
÷
16
Ref
VCO
÷
4
PLL
800 – 1800 MHz
FB
÷
0 TO
÷
511
9-BIT M-DIVIDER
9
÷
1
÷
2
÷
4
÷
8
00
01
10
11
OE
f
OUT
f
OUT
SYNC
TEST
2
N-LATCH
3
T-LATCH
TEST
V
CC
P_LOAD
S_LOAD
LE
P/S
M-LATCH
0
BITS 5-13
S_DATA
S_CLOCK
V
CC
M[0:8]
N[1:0]
OE
1
BITS 3-4
0
14-BIT SHIFT REGISTER
1
BITS 0-2
Figure 1. MPC9229 Logic Diagram
M[8]
M[7]
M[6]
M[5]
18
TEST
GND
GND
f
OUT
V
CC
f
OUT
V
CC
S_CLOCK
S_DATA
S_LOAD
V
CC_PLL
NC
NC
XTAL_IN
25
26
27
28
1
2
3
4
5
XTAL_OUT
24
23
22
21
20
19
18
17
16
24
N[1]
N[0]
M[8]
M[7]
M[6]
M[5]
M[4]
GND
TEST
V
CC
V
CC
GND
f
OUT
f
OUT
V
CC
25
26
27
28
29
30
31
32
1
23
22
21
20
19
M[4]
17
16
15
14
NC
M[3]
M[2]
M[1]
M[0]
P_LOAD
OE
XTAL_OUT
13
12
11
10
9
8
XTAL_IN
N[1]
MPC9229
15
14
13
12
N[0]
3
NC
MPC9229
6
OE
7
P_LOAD
8
M[0]
9
M[1]
10
M[2]
11
M[3]
2
4
5
6
7
S_CLOCK
S_DATA
NC
S_LOAD
V
CC_PLL
Figure 2. MPC9229 28-Lead PLCC Pinout
(Top View)
Figure 3. MPC9229 32-Lead LQFP Pinout
(Top View)
MPC9229 REVISION 3 AUGUST 6, 2009
2
V
CC_PLL
©2009 Integrated Device Technology, Inc.
NC
MPC9229 Data Sheet
Table 1. Pin Configurations
Pin
XTAL_IN, XTAL_OUT
f
OUT
, f
OUT
TEST
S_LOAD
I/O
—
Output
Output
Input
Default
—
—
—
0
Type
Analog
LVPECL
LVCMOS
LVCMOS
Crystal oscillator interface
Differential clock output
400MHZ LOW VOLTAGE PECL CLOCK SYNTHESIZER
Function
Test and device diagnosis output
Serial configuration control input
This inputs controls the loading of the configuration latches with the contents
of the shift register. The latches will be transparent when this signal is high,
thus the data must be stable on the high-to-low transition
Parallel configuration control input
This input controls the loading of the configuration latches with the content of
the parallel inputs (M and N). The latches will be transparent when this signal
is low, thus the parallel data must be stable on the low-to-high transition of
P_LOAD. P_LOAD is state sensitive
Serial configuration data input
Serial configuration clock input
Parallel configuration for PLL feedback divider (M).
M is sampled on the low-to-high transition of P_LOAD.
Parallel configuration for Post-PLL divider (N)
N is sampled on the low-to-high transition of P_LOAD
Output enable (active high).
The output enable is synchronous to the output clock to eliminate the
possibility of runt pulses on the f
OUT
output. OE = L low stops f
OUT
in the logic
low state (f
OUT
= L, f
OUT
= H)
Negative power supply (GND).
Positive power supply for I/O and core. All V
CC
pins must be connected to
the positive power supply for correct operation.
PLL positive power supply (analog power supply).
P_LOAD
Input
1
LVCMOS
S_DATA
S_CLOCK
M[0:8]
N[1:0]
OE
Input
Input
Input
Input
Input
0
0
1
1
1
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
GND
V
CC
V
CC_PLL
Supply
Supply
Supply
Supply
Supply
Supply
Ground
V
CC
V
CC
Table 2. Output Frequency Range and Pll Post-Divider N
N
1
0
0
1
1
0
0
1
0
1
Output Division
1
2
4
8
Output Frequency Range
200 – 400 MHz
100 – 200 MHz
50 – 100 MHz
25 – 50 MHz
MPC9229 REVISION 3 AUGUST 6, 2009
3
©2009 Integrated Device Technology, Inc.
MPC9229 Data Sheet
Table 3. General Specifications
Symbol
V
TT
MM
HBM
LU
C
IN
θ
JA
Characteristics
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Latch-Up Immunity
Input Capacitance
LQFP 32 Thermal Resistance Junction to Ambient
JESD 51-3, Single Layer Test Board
Min
—
200
2000
200
—
—
83.1
73.3
68.9
63.8
57.4
59.0
54.4
52.5
50.4
47.8
—
23.0
Typ
V
CC
–2
—
—
—
4.0
400MHZ LOW VOLTAGE PECL CLOCK SYNTHESIZER
Max
—
—
—
—
—
86.0
75.4
70.9
65.3
59.6
60.6
55.7
53.8
51.5
48.8
26.3
Unit
V
V
V
mA
pF
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
—
—
—
—
Condition
Inputs
Natural Convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
Natural Convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
MIL-SPEC 883E
Method 1012.1
JESD 51-6, 2S2P Multilayer Test Board
θ
JC
LQFP 32 Thermal Resistance Junction to Case
Table 4. Absolute Maximum Ratings
(1)
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
S
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
Characteristics
Min
–0.3
–0.3
–0.3
—
—
–65
Max
3.9
V
CC
+ 0.3
V
CC
+ 0.3
±20
±50
125
Unit
V
V
V
mA
mA
°C
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 5. DC Characteristics
(V
CC
= 3.3 V ± 5%, T
A
= 0°C to +70°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
LVCMOS Control Inputs (P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1], OE)
V
IH
V
IL
I
IN
V
OH
V
OL
V
OH
V
OL
I
CC_PLL
I
CC
Input High Voltage
Input Low Voltage
Input Current
(1)
Output High Voltage
(3)
Output Low Voltage
(3)
Output High Voltage
(3)
Output Low Voltage
(3)
2.0
—
—
—
—
—
V
CC
+ 0.3
0.8
±200
V
V
µA
LVCMOS
LVCMOS
V
IN
= V
CC
or GND
LVPECL
LVPECL
Differential Clock Output f
OUT(2)
V
CC
–1.02
V
CC
–1.95
2.0
—
—
—
V
CC
–0.74
V
CC
–1.60
—
0.55
V
V
Test and Diagnosis Output TEST
—
—
V
V
I
OH
= –0.8 mA
I
OL
= 0.8 mA
V
CC_PLL
Pins
All V
CC
Pins
Supply Current
Maximum PLL Supply Current
Maximum Supply Current
—
—
—
—
20
100
mA
mA
1. Inputs have pull-down resistors affecting the input current.
2. Outputs terminated 50
Ω
to V
TT
= V
CC
–2 V.
3. The MPC9229 TEST output levels are compatible to the MC12429 output levels.
MPC9229 REVISION 3 AUGUST 6, 2009
4
©2009 Integrated Device Technology, Inc.
MPC9229 Data Sheet
Table 6. AC Characteristics
(V
CC
= 3.3 V ± 5%, T
A
= 0°C to +70°C)
(1)
Symbol
f
XTAL
f
VCO
f
MAX
Characteristics
Crystal Interface Frequency Range
VCO Frequency Range
(2)
Output Frequency
N = 00 (÷ 1)
N = 01 (÷ 2)
N = 10 (÷ 4)
N = 11 (÷ 8)
Min
10
800
200
100
50
25
45
0.05
0
50
20
20
20
20
20
—
Typ
—
—
—
400MHZ LOW VOLTAGE PECL CLOCK SYNTHESIZER
Max
20
1600
400
200
100
50
55
0.3
10
—
—
Unit
MHz
MHz
MHz
MHz
MHz
MHz
%
ns
MHz
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ms
—
—
—
Condition
DC
t
r
, t
f
f
S_CLOCK
t
P,MIN
t
S
Output Duty Cycle
Output Rise/Fall Time
Serial Interface Programming Clock Frequency
(3)
Minimum Pulse Width
Setup Time
(S_LOAD, P_LOAD)
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
S_DATA to S_CLOCK
M, N to P_LOAD
N = 00 (÷ 1)
N = 01 (÷ 2)
N = 10 (÷ 4)
N = 11 (÷ 8)
N = 00 (÷ 1)
N = 01 (÷ 2)
N = 10 (÷ 4)
N = 11 (÷ 8)
50
—
—
—
—
—
20% to 80%
—
—
—
t
S
t
JIT(CC)
Hold Time
Cycle-to-Cycle Jitter
—
—
—
90
130
160
190
70
120
140
170
10
—
—
t
JIT(PER)
Period Jitter
—
—
—
t
LOCK
Maximum PLL Lock Time
—
—
—
1. AC characteristics apply for parallel output termination of 50
Ω
to V
TT
.
2. The input frequency f
XTAL
and the PLL feedback divider M must match the VCO frequency range: f
VCO
= f
XTAL
⋅
M
÷
4.
3. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used
as test clock in test mode 6. Refer to
Applications Information
for more details.
MPC9229 REVISION 3 AUGUST 6, 2009
5
©2009 Integrated Device Technology, Inc.
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