SIW3500DIF1SR datasheet, PDF - EEWORLD Datasheet

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SIW3500DIF1SR: DescriptionTelecom Circuit, 1-Func, CMOS, PBGA94, GREEN, KNOWN GOOD DIE, 94 PIN; CategoryWireless rf/communication Telecom circuit; File Size796KB，28 Pages; ManufacturerQorvo; Websitehttps://www.qorvo.com; Environmental Compliance

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SIW3500DIF1SR Overview

Telecom Circuit, 1-Func, CMOS, PBGA94, GREEN, KNOWN GOOD DIE, 94 PIN

SIW3500DIF1SR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Qorvo
Parts packaging code	DIE
package instruction	VFBGA,
Contacts	94
Reach Compliance Code	compliant
JESD-30 code	S-PBGA-B94
JESD-609 code	e2
length	3.7 mm
Number of functions	1
Number of terminals	94
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Package shape	SQUARE
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	0.415 mm
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	TELECOM CIRCUIT
Temperature level	INDUSTRIAL
Terminal surface	TIN SILVER
Terminal form	BALL
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.7 mm

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Preliminary

Features

CLK_REQ_OUT

CLK_REQ_IN

SiW3500

ULTIMATEBLUE™

Bluetooth® SoC

ADDRESS BUS

• Meets all Bluetooth V1.2 and V2.0

qualification requirements.

• Uses standard 0.18-micron CMOS

manufacturing process technology.

• Supports standard and 3-wire (HCI)

transport layer modes with an

integrated UART-based Host Control

Interface.

• Provides improved receiver-blocking

performance due to direct-conversion

RF architecture.

• Permits I/O voltage supply range

from 1.62 V to 3.63 V.

• Provides -85 dBm receiver sensitivity

and +2 dBm transmitter power

(typical).

• Simplifies system design challenges

with integrated analog and digital

voltage regulators.

• Eliminates additional external

impedance matching components

with a 50

Ω

RF I/O.

• Permits flexible reference clock

source options including crystal or

direct input from the host platform.

• Delivers consistent performance from

-40° to +85°C due to internal

temperature compensated

transmitter and receiver circuits.

PLL

Control

Clock Distribution

LNA

Voltage Regulators and

Power Distribution

Optional flash interface

ADC

Internal

50-Ohm

Match

Network

ADC

PLL

Synthesizer

Power

Control

DRIVER

DAC

Aux ADC

DAC

GFSK

Modem

Bluetooth

Link

Controller

ARM7TDMI®

Processor

CS, OE and WE

UART

Multi Function

I/Os

Audio CODEC

Interface

XTAL_P/CLK

XTAL_N

VBATT_ANA

CHG_PUMP

VBATT_DIG

RF_I/O

Data SRAM

Firmware

ROM

Block Diagram

Product Description

The UltimateBlue SiW3500™ is an RF System on Chip (SoC) that combines

a 2.4-GHz transceiver, baseband processor, and protocol stack software for

Bluetooth® wireless technology. Due to its low power CMOS process, the

SiW3500 is ideally suited for applications such as mobile phones, audio

headsets, and other embedded products.

The SiW3500 integrates an ARM7TDMI

processor for software execution

from either internal ROM or external FLASH memory. The standard

SiW3500 ROM contains the Bluetooth lower layer stack software including

the HCI transport driver.

The SiW3500 is packaged in a 6-by-6-mm, Pb-free, 96-pin, VFBGA that

meets RoHS and Green requirements. Known Good Die (KGD) is available

for special applications.

Applications

• Mobile phones and smart phones.

• Bluetooth audio headset.

• Bluetooth hands-free kit.

Ordering Information

SiW3500

UltimateBlue™ SoC

See page 27 for details.

Optimum Technology Matching® Applied

Si BJT

Si Bi-CMOS

GaInP/HBT

GaAs HBT

SiGe HBT

GaN HEMT

GaAs MESFET

Si CMOS

SiGe Bi-CMOS

RF Micro Devices, Inc.

7628 Thorndike Road

Greensboro, NC 27409, USA

Tel (336) 664 1233

Fax (336) 664 0454

http://www.rfmd.com

60 0066 R00JIrf SiW3500 UltimateBlue SoC DS

June 27, 2005

DATA BUS

VCC_OUT

VDD_C

VTUNE

VDD_P

• Combines a 2.4-GHz transceiver,

baseband processor, and 32-bit

ARM7TDMI® processor in a single

RF System on Chip (SoC).

1 of 28

SiW3500

Radio Features

•

Preliminary

RF System on Chip (SoC) for Bluetooth wireless technology combining a 2.4-GHz transceiver, baseband processor,

and protocol stack ROM.

Manufactured using standard 0.18 m CMOS process technology.

Direct conversion RF architecture improves receiver-blocking performance.

I/O voltage supply can range from 1.62 V to 3.63 V.

-85 dBm receiver sensitivity and +2 dBm transmitter power typical performance specifications.

Integrated analog and digital voltage regulators simplify system design.

Ω

RF I/O does not need any additional external impedance matching components.

Flexible reference clock source options including crystal or direct input from the host platform.

Internal temperature compensated transmitter and receiver circuits deliver consistent performance from -40° to

+85°C.

Hardware based GFSK modem and packet processing contributes to lower system current consumption with minimal

software overhead.

ARM7TDMI processor efficiently executes all protocol stack and application software.

UART based Host Control Interface (HCI) transport layer supports standard and 3-wire modes.

Software execution from either internal ROM or external FLASH memory. The SiW3500 features a ROM patch

mechanism that allows substituting small portions of ROM code with code either downloaded from the host or stored

in external EEPROM.

Extensive multi function I/Os allow flexible product configurations.

Auxiliary analog-to-digital converter (ADC) is available for applications such as battery level detection.

Full-featured lower layer Bluetooth protocol stack software up to the host interface (HCI).

Bluetooth V1.2 and V2.0 qualified including all mandatory and optional features such as power class 1 operation,

power control, and multi-slot packets.

Full Bluetooth connection capabilities with support for piconet and scatternet modes and device scanning during SCO

connection.

Able to establish up to 3 SCO connections simultaneously.

Supports low power connection states such as hold, sniff, and park modes with selectable sniff intervals.

Full support of Bluetooth test modes for use during production.

Verified HCI command level compatibility with multiple upper layer software stacks.

Proprietary channel assessment algorithm provides fast and accurate determination of occupied channels for use in

AFH mode.

In addition to AFH, UltimateBlue Coexistence Technology is part of the baseline protocol stack. UltimateBlue

coexistence minimizes interference to 802.11b/g products.

The Channel Quality Driven Data Rate (CQDDR) feature optimizes data transfer in noisy or weak signal

environments.

Full selection of upper layer protocol stack software and profiles available for license and customization.

Baseband Features

•

Standard Protocol Stack Features

Additional Protocol Stack Features

2 of 28

60 0066 R00JIrf SiW3500 UltimateBlue SoC DS

SiW3500

Preliminary

External Memory Interface

The SiW3500 does not require additional memory for standard below HCI protocol functions. An external memory

interface is available for execution of protocol stack software from FLASH memory if desired. If external FLASH memory

will be used, the read access time of the device must be 100 ns or less.

Auxiliary UART

The SiW3500 can be configured and enabled with an auxiliary UART port. This UART port can be used for debug

depending on the application software.

Signal

AUX_TXD

AUX_RXD

AUX_CTS

AUX_RTS

TX Data

RX Data

Clear To Send

Request To Send

Description

External Power Amplifier Interface

The SiW3500 supports the use of an external power amplifier for +20 dBm designs. When enabled, these signals

provide an integrated interface for the control of an external PA.

Signal

IDAC

TX_RX_SWITCH

Description

Power control to external PA. This output provides a variable current source that

can be used to control the external PA. Leave unconnected if not used

Output signal used to indicate the state of the radio. This could be used as a

direction control for the PA. The polarity is programmable with the default set as:

Low = Transmit; High = Receive.

Power Management

The HOST_WAKEUP and EXT_WAKE signals are used for power management control of the SiW3500.

HOST_WAKEUP is an output signal used to wake up the host. EXT_WAKE is an input signal used by the host to wake

up the SiW3500 from sleep mode.

For control of the reference clock source, CLOCK_REQ_IN and CLOCK_REQ_OUT can be made available to turn on/off

an external reference clock source.

General-Purpose Analog to Digital Converter (ADC)

The SiW3500 incorporates a general-purpose ADC that can be enabled to sample external analog voltage. The ADC

has an 8-bit resolution.

External EEPROM Controller and Interface

This interface is intended for communication to an optional EEPROM when using the SiW3500 in ROM mode. The

EEPROM is not required for configurations with external flash. The EEPROM is the non-volatile memory (NVM) in the

system and contains the system configuration parameters such as the Bluetooth device address, the CODEC type, as

well as other parameters. These default parameters are set at the factory, and some parameters will change depending

on the system configuration. Optionally, the memory parameters can be downloaded from the host processor at boot up

eliminating the need for EEPROM. Please consult the Application Support team for details. The EEPROM should have a

serial I

C interface with a minimum size of 2 Kbits and 16-byte page write buffer capabilities.

General System Requirements

System Reference Clock

The SiW3500 chip can use either an external crystal or a reference clock as the system clock input. A partial list of

supported frequencies (in MHz) includes: 9.6, 12, 12.8, 13, 14.4, 15.36, 16, 16.8, 19.2, 19.68, 19.8, 26, 32, 38.4, and 48.

For other frequencies, please contact Applications Support. The system reference crystal/clock must have an accuracy

of ±20 PPM or better to meet the Bluetooth specification.

4 of 28

60 0066 R00JIrf SiW3500 UltimateBlue SoC DS

Preliminary

SiW3500

Low Power Clock

For the Bluetooth low power clock, a 32.768-kHz crystal can be used to drive the SiW3500 oscillator circuit, or alterna-

tively, a 32.768-kHz reference clock signal can be used instead of a crystal. If the lowest power consumption is not

required during low-power modes such as sniff, hold, park, and idle modes, the 32.768-kHz crystal may be omitted in the

design. If the 32.768-kHz clock source is used, the clock source should be connected to the CLK32_IN pin via an AC-

coupling capacitor (100 pF or greater), and its amplitude must meet the following requirements:

•

For AC-coupled via 100 pF or greater (peak-to-peak voltage):

400 mV

P-P

< CLK32_IN < V

DD_C

Note: It is recommended to keep CLK32_IN voltage to 1 Vp-p maximum to minimize the I/O power supply current when the

VBATT_ANA and VBATT_DIG are shut off while VDD_P and VDD_P_ALT are still powered. The CLK32_OUT can be left open.

However, connecting the CLK32_OUT pin to either VDD_P or GND through a 100 nF capacitor improves the circuit's sensitivity

slightly if operating near the low end of the CLK32_IN range above.

Note:

Power Supply Description

The SiW3500 operates at 1.8 V core voltage for internal analog and digital circuits. The chip has internal analog and

digital voltage regulators simplifying power supply requirements to the chip. The internal voltage regulators can be

supplied directly from a battery or from other system voltage sources. Optionally, the internal regulators can be by-

passed if a 1.8 V regulated source is available on the system.

Function

Regulator input pin

Regulator output pin

Internal Analog Regulator

BATT_ANA

= 2.3 to 3.63 V

CC_OUT

= 1.8 V

Internal Digital Regulator

BATT_DIG

= 2.3 to 3.63 V

DD_C

= 1.8 V

Internal Regulator Used

Function

Circuit voltage supply pin

Analog Core Circuits

= 1.8 V

Digital Core Circuits

DD_C

= 1.8 V

Internal Regulator Bypassed

Note:

Both regulators can be bypassed if external regulation is desired. When bypassing the analog regulator, the V

BATT_ANA

and

CC_OUT

pins must be tied together and the external analog voltage (1.8 V) should be applied to the V

BATT_ANA

pin. When

bypassing the digital regulator, the V

BATT_DIG

pin should be left unconnected and the external digital voltage (1.8 V) should be

applied to V

DD_C

pin.

The power for the I/Os is taken from two separate sources (V

DD_P

and V

DD_P_ALT

). They can range from 1.62 to 3.63

Volts to maintain compatibility with a wide range of peripheral devices. Please check the pin list for the exact pins that are

powered from the V

DD_P

and V

DD_P_ALT

sources.

RF I/O Description

The SiW3500 employs single-ended RF input and output pins for reduced external components. In typical power class 2

(0 dBm nominal) applications, no external matching components are necessary.

On-Chip Memory

The SiW3500 SoC integrates both SRAM and ROM. The ROM is pre-programmed with Bluetooth protocol stack

software (HCI software) and boot code that executes automatically upon reset. The boot code serves to control the boot

sequence as well as to direct the execution to the appropriate memory for continued operation.

60 0066 R00JIrf SiW3500 UltimateBlue SoC DS

5 of 28

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