Intel
®
Celeron
®
Processor for the PGA370
Socket up to 1.40 GHz on 0.13 Micron
Process
Datasheet
Product Features
s
s
s
s
s
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Available at 1.4 GHz, 1.30 GHz, 1.20 GHz,
1.10A GHz, 1A GHz and 900 MHz with
100 MHz system bus
256 KB on-die Level 2 (L2) cache with Error
Correcting Code (ECC))
Dual Independent Bus (DIB) architecture:
Separate dedicated external System Bus and
dedicated internal high-speed cache bus
Internet Streaming SIMD Extensions for
enhanced video, sound and 3D performance
Binary compatible with applications running
on previous members of the Intel
microprocessor line
Dynamic execution micro architecture
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Power Management capabilities
— System Management mode
— Multiple low-power states
Optimized for 32-bit applications running on
advanced 32-bit operating systems
Flip Chip Pin Grid Array (FC-PGA2) packaging
technology
Integrated high performance 16 KB instruction
and 16 KB data, nonblocking, level one cache
Integrated Full Speed level two cache allows for
low latency on read/store operations
Error-correcting code for System Bus data
The Intel
®
Celeron
®
processor is designed for uni-processor based Value PC desktops and is binary
compatible with previous generation Intel architecture processors. The Intel Celeron processor provides
good performance for applications running on advanced operating systems such as Windows* 95/98,
WindowsNT*, Windows* 2000, WindowsXP* and UNIX*. This is achieved by integrating the best
attributes of Intel processors—the dynamic execution performance of the P6 microarchitecture plus the
capabilities of MMX™ technology—bringing a balanced level of performance to the Value PC market
segment. The Intel Celeron processor offers the dependability you would expect from Intel at an
exceptional value. Systems based on Intel Celeron processors also include the latest features to simplify
system management and lower the cost of ownership for small business and home environments.
May 2002
Order Number:
298596-004
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
®
Celeron
®
processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2002
Intel, Celeron, MMX, Pentium, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States
and other countries.
*Other names and brands may be claimed as the property of others.
Datasheet
Intel
®
Celeron
®
Processor for PGA370 up to 1.40 GHz on 0.13
µ
Process
Contents
1.0
Introduction......................................................................................................................... 9
1.1
Terminology.........................................................................................................10
1.1.1 Package and Processor Terminology ....................................................10
1.1.2 Processor Naming Convention...............................................................11
Related Documents.............................................................................................12
Processor System Bus and V
REF .......................................................................................... 13
Clock Control and Low Power States..................................................................14
2.2.1 Normal State—State 1 ...........................................................................15
2.2.2 AutoHALT Powerdown State—State 2...................................................15
2.2.3 Stop-Grant State—State 3 .....................................................................15
2.2.4 HALT/Grant Snoop State—State 4 ........................................................15
2.2.5 Sleep State—State 5..............................................................................16
2.2.6 Deep Sleep State—State 6 ....................................................................16
2.2.7 Clock Control..........................................................................................17
Power and Ground Pins ......................................................................................17
2.3.1 Phase Lock Loop (PLL) Power...............................................................17
Decoupling Guidelines ........................................................................................18
2.4.1 Processor VCC
CORE
Decoupling............................................................18
Processor System Bus Clock and Processor Clocking .......................................19
Voltage Identification ...........................................................................................19
Processor System Bus Unused Pins...................................................................21
Processor System Bus Signal Groups ................................................................22
2.8.1 Asynchronous vs. Synchronous for System Bus Signals .......................23
2.8.2 System Bus Frequency Select Signals ..................................................24
Test Access Port (TAP) Connection....................................................................25
Maximum Ratings................................................................................................25
Processor Voltage Level Specifications ..............................................................25
AGTL System Bus Specifications........................................................................30
System Bus Timing Specifications ......................................................................31
BCLK/BCLK# & PICCLK Signal Quality Specifications and
Measurement Guidelines ....................................................................................41
AGTL Signal Quality Specifications and Measurement Guidelines.....................42
3.2.1 Overshoot/Undershoot Guidelines .........................................................43
3.2.2 Overshoot/Undershoot Magnitude .........................................................44
3.2.3 Overshoot/Undershoot Pulse Duration...................................................44
3.2.4 Activity Factor .........................................................................................44
3.2.5 Reading Overshoot/Undershoot Specification Tables............................45
3.2.6 Determining if a System Meets the Overshoot/Undershoot
Specifications .........................................................................................46
Non-AGTL Signal Quality Specifications and Measurement Guidelines.............47
3.3.1 Overshoot/Undershoot Guidelines .........................................................48
3.3.2 Ringback Specification ...........................................................................48
3.3.3 Settling Limit Guideline...........................................................................49
1.2
2.0
2.1
2.2
Electrical Specifications....................................................................................................13
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
3.0
3.1
3.2
Signal Quality Specifications ............................................................................................41
3.3
Datasheet
3
Intel
®
Celeron
®
Processor for PGA370 up to 1.40 GHz on 0.13
µ
Process
3.4
VTT_PWRGD Signal Quality Specification ......................................................... 49
3.4.1 Transition region .................................................................................... 49
3.4.2 Transition time........................................................................................ 50
3.4.3 Noise ...................................................................................................... 50
Thermal Specifications........................................................................................ 51
4.1.1 THERMTRIP# Requirement................................................................... 51
4.1.2 Thermal Diode........................................................................................ 52
Thermal Metrology .............................................................................................. 52
FC-PGA2 Mechanical Specifications .................................................................. 53
Recommended Mechanical Keep-Out Zones ..................................................... 55
Processor Markings ............................................................................................ 56
Processor Signal Listing...................................................................................... 57
Mechanical Specifications................................................................................... 68
6.1.1 Mechanical Specifications for the FC-PGA2 Package ........................... 68
6.1.2 Boxed Processor Heatsink Weight......................................................... 70
Thermal Specifications........................................................................................ 70
6.2.1 Boxed Processor Cooling Requirements ............................................... 70
6.2.2 Boxed Processor Thermal Cooling Solution Clip ................................... 71
Electrical Requirements for the Boxed Processor............................................... 71
6.3.1 Electrical Requirements ......................................................................... 71
Alphabetical Signals Reference .......................................................................... 73
Signal Summaries ............................................................................................... 80
4.0
Thermal Specifications and Design Considerations......................................................... 51
4.1
4.2
5.0
5.1
5.2
5.3
5.4
6.0
6.1
Mechanical Specifications................................................................................................ 53
Boxed Processor Specifications....................................................................................... 68
6.2
6.3
7.0
Processor Signal Description ........................................................................................... 73
7.1
7.2
4
Datasheet
Intel
®
Celeron
®
Processor for PGA370 up to 1.40 GHz on 0.13
µ
Process
List of Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Integrated Heat Spreader (IHS) ............................................................................ 9
AGTL Bus Topology in a Uniprocessor Configuration.........................................14
Stop Clock State Machine ...................................................................................14
PLL Filter Specification........................................................................................18
Differential/Single-Ended Clocking Example.......................................................19
V
TT
Power Good and Bus Select Interconnect Diagram .....................................21
BSEL[1:0] Example for a System Design............................................................24
Vcc Static and Transient Tolerance ....................................................................28
Clock Waveform ..................................................................................................36
BCLK/BCLK#, PICCLK, and TCK Generic Clock Waveform ..............................37
System Bus Valid Delay Timings ........................................................................37
System Bus Setup and Hold Timings..................................................................38
System Bus Reset and Configuration Timings....................................................38
Platform Power-On Sequence and Timings ........................................................39
Power-On Reset and Configuration Timings.......................................................39
Test Timings (TAP Connection) ..........................................................................40
Test Reset Timings .............................................................................................40
BCLK/BCLK#, PICCLK Generic Clock Waveform at the Processor Pins ...........42
Low to High AGTL Receiver Ringback Tolerance...............................................43
Maximum Acceptable AGTL Overshoot/Undershoot Waveform .........................47
Non-AGTL Overshoot/Undershoot, Settling Limit, and Ringback ......................47
Noise Estimation .................................................................................................50
Package Dimensions...........................................................................................53
Volumetric Keep-Out ...........................................................................................55
Component Keep-Out .........................................................................................55
Top Side Processor Markings .............................................................................56
Processor Pinout ................................................................................................57
Conceptual Boxed Processor for the PGA370 Socket ........................................68
Comparison between FC-PGA and FC-PGA2 package......................................69
Side View of Space Requirements for the Boxed Processor ..............................69
Dimensions of Mechanical Step Feature in Heatsink Base.................................70
Thermal Airspace Requirement for all Boxed Processor Fan
Heatsinks in the PGA370 Socket ........................................................................71
Boxed Processor Fan Heatsink Power Cable Connector Description.................72
Motherboard Power Header Placement Relative to the Boxed Processor..........72
Datasheet
5
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