HT83FXX
Flash Type Voice OTP MCU
Technical Document
·
Application Note
-
HA0075E MCU Reset and Oscillator Circuits Application Note
Features
·
Operating voltage: 2.7V~3.6V
·
System clock: 4MHz~8MHz
·
Crystal and RC system oscillator
·
12 I/O pins
·
I
2
C/SPI Bus Serial Interface, shared with PB
·
2K´15 OTP Program Memory
·
Between 2M´8 bit and 128K´8 bit flash type data
·
4-level subroutine nesting
·
2.7V Low voltage detection, tolerance 5%
·
Integrated LDO regulator in
HT83F10P/20P/40P/60P/80P
·
Power-down function and wake-up feature reduce
power consumption
·
Up to 1ms (0.5ms) instruction cycle with 4MHz (8MHz)
memory
·
80´8 Data Memory
·
Two 8-bit programmable timer counter with 8-stage
system clock at V
DD
= 3.6V
·
63 powerful instructions
·
One reset pin
·
Flash Data Memory can be re-programmed up to
prescaler and one time base counter
·
12-bit high quality voltage type D/A output
·
PWM circuit direct drive speaker
·
Watchdog Timer function
100,000 times
·
Flash Data Memory data retention > 10 years
·
44-pin QFP package
General Description
The flash type voice series of MCUs have OTP type
Program Memory and Flash type Voice Memory.
The devices are 8-bit high performance microcontrollers
which include a voice synthesizer and tone generator.
They are designed for applications which require multiple
I/Os and sound effects, such as voice and melody. The
devices can provide various sampling rates and beats,
tone levels, tempos for speech synthesizer and melody
generator.
They also include two integrated high quality, voltage
type DAC outputs and voltage type PWM outputs.
The devices are excellent solutions for versatile voice
and sound effect product applications with their efficient
MCU instructions providing the user with programming
capability for powerful custom applications. The system
frequency can be up to 8MHz at an operating voltage of
2.7V and include a power-down function to reduce
power consumption.
The MCU flash voice memory capacity ranges from
2M´8 bit to 128K´8 bit, into which the user can down-
load their voice data repeatedly.
Rev. 1.10
1
January 21, 2010
HT83FXX
Selection Table
The devices include a comprehensive range of features, with most features common to all devices. The main features
distinguishing them are Flash Voice Memory capacity. The functional differences between the devices are shown in the
following table.
OTP
Program
Memory
2K´15
Flash
Voice
Memory
128K´8
I
2
C/
SPI
Ö
Part No.
HT83F10
HT83F10P
HT83F20
HT83F20P
HT83F40
HT83F40P
HT83F60
HT83F60P
HT83F80
HT83F80P
VDD
2.7V~3.6V
3.3V
2.7V~3.6V
3.3V
2.7V~3.6V
3.3V
2.7V~3.6V
3.3V
2.7V~3.6V
3.3V
VIN
¾
3.6V~24V
¾
3.6V~24V
¾
3.6V~24V
¾
3.6V~24V
¾
3.6V~24V
Data
Memory
Voice
Capacity
I/O
8-bit
Timer
D/A
Package
Types
80´8
32sec
12
2
12-bit,
PWM
12-bit,
PWM
12-bit,
PWM
12-bit,
PWM
12-bit,
PWM
44QFP
2K´15
80´8
256K´8
64sec
12
2
Ö
44QFP
2K´15
80´8
512K´8
128sec
12
2
Ö
44QFP
2K´15
80´8
1024K´8
256sec
12
2
Ö
44QFP
2K´15
80´8
2048K´8
512sec
12
2
Ö
44QFP
Note: For devices that exist in more than one package formats, the table reflects the situation for the larger package.
Voice length is estimated by 32K-bit data rate, or 8K sampling rate and 4 bit ADPCM compress mode.
Block Diagram
W a tc h d o g
T im e r
8 - b it
R IS C
M C U
C o re
L o w
V o lta g e
D e te c tio n
P W M
S P I
F u n c tio n
I
2
C
F u n c tio n
H T 8 3 F 1 0 P /2 0 P /4 0 P /6 0 P /8 0 P
L D O
S ta c k
W a tc h d o g
T im e r O s c illa to r
R e s e t
C ir c u it
In te rru p t
C o n tr o lle r
R C /C ry s ta l
O s c illa to r
O T P R O M
P ro g ra m
M e m o ry
F la s h D a ta
M e m o ry
R A M D a ta
M e m o ry
I/O
P o rts
8 - b it
T im e r
D /A
C o n v e rte rs
Rev. 1.10
2
January 21, 2010
HT83FXX
Pin Assignment
H O L
N
C
N
S
N
N
W
V S S
N
S C
O
O
C
C
C
C
C
C
D
P
K
S
P
K
S
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
4 4 4 3 4 2 4 1
F
F
4 0 3 9 3 8 3 7 3 6 3 5 3 4
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
4 4 4 3 4 2 4 1
4 0 3 9 3 8 3 7 3 6 3 5 3 4
C
C
C
C
D
H O L
N
C
N
S
N
N
W
V S S
N
S C
P
P
P
P
P
P
P
P
P
P
S I
A 7
A 6
A 5
A 4
A 3
A 2
A 1
A 0
B 0
B 1
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
H T 8 3 F 1 0 /2 0 /4 0 /6 0 /8 0
4 4 Q F P -A
V D D
N C
N C
V S S
P W M
P W M
V D D
V D D
A U D
V S S
O S C
P
A
F
P
P
P
2
P
1
P
P
A
P
P
P
2
P
P
S I
A 7
A 6
A 5
A 4
A 3
A 2
A 1
A 0
B 0
B 1
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
H T 8 3 F 1 0 P /2 0 P /4 0 P /6 0 P /8 0 P
4 4 Q F P -A
V D D F
L D O _ O U T
L D O _ IN
V S S P
P W M 2
P W M 1
V D D P
V D D A
A U D
V S S A
O S C 2
Pin Description
Pin Name
I/O
Options
Wake-up,
Pull-high
or None
Description
Bidirectional 8-bit I/O port, Each bit can be configured as a wake-up input by
configuration option. Software instructions determine if the pin is a CMOS out-
put or Schmitt trigger input. Configuration options determine which pins on this
port have pull-high resistors.
Bidirectional 4-bit I/O port. Each bit can be configured as a wake-up input by
configuration option. Software instructions determine if the pin is a CMOS out-
put or Schmitt trigger input. Configuration options determine which pins on this
port have pull-high resistors. Pins PB0~PB3 are pin-shared with SPI flash
control and I
2
C control pins SDO/SDA, SCK/SCL, SDI and SCS.
Data output pin
Clock output pin.
Data input pin.
Select signal.
Audio output for driving external transistor or power amplifier.
PWM circuit direct speaker drive
Schmitt trigger reset input. Active low
OSC1, OSC2 are connected to an external RC network or external crystal, de-
termined by configuration option, for the internal system clock. If the RC sys-
tem clock option is selected, pin OSC2 can be used to measure the system
clock at 1/4 frequency.
Positive digital power supply
Negative digital power supply, ground
PWM negative power supply, ground
PWM positive power supply
Negative DAC circuit power supply, ground
Positive DAC circuit Power supply
O S C 1
R E S
V D D _ P B IO
V D D
V S S
S C S
D I
C L K
D O
P B 3
P B 2
O S C 1
R E S
V D D _ P B IO
V D D
V S S
S C S
D I
C L K
D O
P B 3
P B 2
PA0~PA7
I/O
PB0/SDO/SDA
PB1/SCK/SCL
PB2/SDI
PB3/SCS
DO
CLK
DI
SCS
AUD
PWM1, PWM2
RES
OSC1
OSC2
VDD
VSS
VSSP
VDDP
VSSA
VDDA
I/O
Pull-high
or None
O
O
I
O
O
O
I
¾
¾
¾
¾
CMOS
¾
¾
Crystal
or RC
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
Rev. 1.10
3
January 21, 2010
HT83FXX
Pin Name
VDD_PBIO
LDO_OUT
LDO_IN
CS
SI
SO
SCK
HOLD
WP
VDDF
VSSF
I/O
¾
O
I
I
I
O
I
I
I
¾
¾
Options
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
Description
PB I/O external positive power supply (determine by option)
LDO output
LDO input
Flash data memory chip select pin
Flash data memory data input pin
Flash data memory data output pin
Flash data memory clock input pin
Hold, pause the device without deselecting Flash data memory
Flash data memory write protect pin
Positive Flash data memory Power supply
Negative Flash data memory Power supply, ground
Note: Each pin on PA can be programmed through a configuration option to have a wake-up function.
Individual pins can be selected to have pull-high resistors.
Absolute Maximum Ratings
Supply Voltage ...........................V
SS
+2.7V to V
SS
+3.6V
Input Voltage..............................V
SS
-0.3V
to V
DD
+0.3V
I
OL
Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Storage Temperature ..........................-50°C to +125°C
Operating Temperature.........................-40°C to +85°C
I
OH
Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under
²Absolute
Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Test Conditions
Symbol
V
DD
f
SYS
Parameter
V
DD
Operating Voltage
System Frequency
¾
3V
Conditions
f
SYS
=4MHz/8MHz
R
OSC
=275kW
R
OSC
=144kW
I
DD
I
STB1
I
STB2
V
IL1
V
IH1
V
IL2
V
IH2
V
LVD
V
LDO
V
LDO_IN
Operating Current
Standby Current (WDT Off)
Standby Current (WDT On)
Input Low Voltage for I/O Ports
Input High Voltage for I/O Ports
Input Low Voltage (RES)
Input High Voltage (RES)
Low Voltage Detection
LDO Output Voltage
LDO Input Voltage
3V
3V
3V
3V
3V
3V
3V
¾
¾
¾
LVD 2.7V
V
LDO_IN
>3.6V
¾
No load, f
SYS
=4MHz
No load, f
SYS
=8MHz
No load, system HALT
No load, system HALT
¾
¾
¾
¾
2.7
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
2.565
3.2
3.6
¾
4
8
¾
¾
¾
¾
1
2
1.4
2.1
2.700
3.3
¾
3.6
¾
¾
3
5
1
7
¾
¾
¾
¾
2.835
3.4
24
Min.
Typ.
Max.
Ta=25°C
Unit
V
MHz
MHz
mA
mA
mA
mA
V
V
V
V
V
V
V
Rev. 1.10
4
January 21, 2010
HT83FXX
Test Conditions
Symbol
I
LDO
I
OL1
I
OH1
I
OL2
I
OH2
I
AUD
R
PH
Parameter
V
DD
LDO Output Current
I/O Port Sink Current
I/O Port Source Current
PWM1/PWM2 Sink Current
PWM1/PWM2 Sink Current
AUD Source Current
Pull-high Resistance
¾
3V
3V
3V
3V
3V
3V
Conditions
V
LDO_IN
=5.5V
V
OL
=0.1V
DD
V
OH
=0.9V
DD
V
OL
=0.1V
DD
V
OH
=0.9V
DD
V
OH
=0.9V
DD
¾
60
7
-3.5
50
-14.5
¾
20
100
¾
¾
¾
¾
-3
60
¾
¾
¾
¾
¾
¾
100
mA
mA
mA
mA
mA
mA
kW
Min.
Typ.
Max.
Unit
A.C. Characteristics
Test Conditions
Symbol
f
SYS
f
TIMER
t
WDTOSC
t
WDT1
t
WDT2
t
RES
t
SST
t
INT
Parameter
V
DD
System Clock
(RC OSC, Crystal OSC)
Timer Inut Frequency
Watchdog Oscillator Period
Watchdog Time-out Period
(WDT OSC)
Watchdog Time-out Period
(System Clock)
External Reset Low Pulse Width
System Start-up Timer Period
Interrupt Pulse Width
¾
¾
3V
3V
¾
¾
¾
¾
Conditions
2.7V~3.6V
2.7V~3.6V
¾
Without WDT prescaler
Without WDT prescaler
¾
Wake-up from HALT
¾
4
0
45
12
¾
1
¾
1
¾
¾
90
23
1024
¾
1024
¾
8
8
180
45
¾
¾
¾
¾
Min.
Typ.
Max.
Ta=25°C
Unit
MHz
MHz
ms
ms
ms
ms
*t
SYS
ms
Note: *t
SYS
=1/f
SYS
Characteristics Curves
·
R vs. F Chart Characteristics Curves
R v s . F C h a rt
1 0
8
F re q u e n c y (M H z )
6
3 .3 V
4
2
1 5 0
1 9 5
2 8 5
R (k
W
)
3 7 6
4 4 5
Rev. 1.10
5
January 21, 2010
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