Integrated
Circuit
Systems, Inc.
ICS8532BY-01
L
OW
S
KEW
, 1-
TO
-17
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
F
EATURES
•
17 differential 3.3V LVPECL outputs
•
Selectable differential CLK, nCLK or LVPECL clock inputs
•
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
•
Maximum output frequency: 500MHz
•
Translates any single-ended input signal (LVCMOS, LVTTL,
GTL) to 3.3V LVPECL levels with resistor bias on nCLK input
•
Output skew: 50ps (maximum)
•
Part-to-part skew: 250ps (maximum)
•
Propagation delay: 2.5ns (maximum)
•
3.3V operating supply
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
G
ENERAL
D
ESCRIPTION
The ICS8532BY-01 is a low skew, 1-to-17, Dif-
ferential-to-3.3V LVPECL Fanout Buffer and a
HiPerClockS™
member of the HiPerClockS™ family of High Per-
formance Clock Solutions from ICS. The
ICS8532BY-01 has two selectable clock inputs.
The CLK, nCLK pair can accept most standard differential
input levels. The PCLK, nPCLK pair can accept LVPECL,
CML, or SSTL input levels. The clock enable is internally
synchronized to eliminate runt pulses on the outputs during
asynchronous assertion/deassertion of the clock enable pin.
,&6
Guaranteed output and part-to-part skew characteristics make
the ICS8532BY-01 ideal for those clock distribution applica-
tions demanding well defined performance and repeatability.
B
LOCK
D
IAGRAM
CLK_EN
D
Q
CLK
nCLK
PCLK
nPCLK
CLK_SEL
P
IN
A
SSIGNMENT
V
CCO
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
LE
0
1
Q0:Q16
nQ0:nQ16
V
CCO
nc
V
CC
V
CC
CLK
nCLK
CLK_SEL
PCLK
nPCLK
V
EE
CLK_EN
V
EE
V
CCO
1
2
3
4
5
6
7
8
9
52 51 50 49 48 47 46 45 44 43 42 41 40
39
38
37
36
35
10
11
12
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
nQ16
Q16
nQ15
Q15
nQ14
Q14
V
CCO
nQ13
Q13
nQ12
Q12
nQ11
Q11
52-Lead LQFP
10mm x 10mm x 1.4mm body package
Y package
Top View
8532BY-01
www.icst.com/products/hiperclocks.htlm
1
Q0
Q1
ICS8532BY-01
Q2
Q3
Q4
Q5
V
CCO
Q6
nQ6
Q7
nQ7
Q8
nQ8
V
CCO
Q9
nQ9
Q10
nQ10
V
CCO
34
33
32
31
30
29
28
REV. A JUNE 26, 2002
Integrated
Circuit
Systems, Inc.
ICS8532BY-01
L
OW
S
KEW
, 1-
TO
-17
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
Type
Description
Output supply pins.
No connect.
Positive supply pins.
Pulldown Non-inver ting differential clock input.
Inver ting differential clock input.
Clock select input. When HIGH, selects CLK, nCLK inputs.
Pulldown When LOW, selects PCLK, nPCLK inputs.
LVCMOS / LVTTL interface levels.
Pulldown Non-inver ting differential LVPECL clock input.
Pullup
Inver ting differential LVPECL clock input.
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follows clock input.
When LOW, Q outputs are forced low, nQ outputs are forced high.
LVCMOS / LVTTL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Pullup
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 13,
20, 27,
32, 39, 46
2
3, 4
5
6
7
8
9
10, 12
11
14, 15
16, 17
18, 19
Name
V
CCO
nc
V
CC
CLK
nCLK
CLK_SEL
PCLK
nPCLK
V
EE
CLK_EN
nQ16, Q16
nQ15, Q15
nQ14, Q14
Power
Unused
Power
Input
Input
Input
Input
Input
Power
Input
Output
Output
Output
Pullup
21, 22
nQ13, Q13 Output
Differential clock outputs. LVPECL interface levels.
23, 24
nQ12, Q12 Output
Differential clock outputs. LVPECL interface levels.
25, 26
nQ11, Q11 Output
Differential clock outputs. LVPECL interface levels.
28, 29
nQ10, Q10 Output
Differential clock outputs. LVPECL interface levels.
30, 31
nQ9, Q9
Output
Differential clock outputs. LVPECL interface levels.
33, 34
nQ8, Q8
Output
Differential clock outputs. LVPECL interface levels.
35, 36
nQ7, Q7
Output
Differential clock outputs. LVPECL interface levels.
37, 38
nQ6, Q6
Output
Differential clock outputs. LVPECL interface levels.
40, 41
nQ5, Q5
Output
Differential clock outputs. LVPECL interface levels.
42, 43
nQ4, Q4
Output
Differential clock outputs. LVPECL interface levels.
44, 45
nQ3, Q3
Output
Differential clock outputs. LVPECL interface levels.
47, 48
nQ2, Q2
Output
Differential clock outputs. LVPECL interface levels.
49, 50
nQ1, Q1
Output
Differential clock outputs. LVPECL interface levels.
51, 52
nQ0, Q0
Output
Differential clock outputs. LVPECL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
NOTE: Unused output pairs must be terminated.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
CLK, nCLK
Input
Capacitance
PCLK, nPCLK
CLK_EN, CLK_SEL
Input Pullup Resistor
Input Pulldown Resistor
51
51
Test Conditions
Minimum
Typical
Maximum
4
4
4
Units
pF
pF
pF
KΩ
KΩ
8532BY-01
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2
REV. A JUNE 26, 2002
Integrated
Circuit
Systems, Inc.
ICS8532BY-01
L
OW
S
KEW
, 1-
TO
-17
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
Inputs
Outputs
Selected Source
CLK, nCLK
PCLK, nPCLK
CLK, nCLK
Q0:Q16
Disabled; LOW
Disabled; LOW
Enabled
nQ0:nQ16
Disabled; HIGH
Disabled; HIGH
Enabled
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
CLK_EN
0
0
1
CLK_SEL
0
1
0
1
1
PCLK, nPCLK
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1
.
In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described
in Table 3B
.
Disabled
nCLK, nPCLK
CLK, PCLK
Enabled
CLK_EN
nQ0:nQ16
Q0:Q16
F
IGURE
1 - CLK_EN T
IMING
D
IAGRAM
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK or PCLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK or nPCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Q0:Q16
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
nQ0:nQ16
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
NOTE 1: Please refer to the Application Information section "Wiring the Differential Input to Accept Single Ended Levels".
8532BY-01
www.icst.com/products/hiperclocks.htlm
3
REV. A JUNE 26, 2002
Integrated
Circuit
Systems, Inc.
ICS8532BY-01
L
OW
S
KEW
, 1-
TO
-17
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
4.6V
-0.5V to V
CC
+ 0.5V
-0.5V to V
CCO
+ 0.5V
42.3°C/W (0 lfpm)
-65°C to 150°C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CCx
Inputs, V
I
Outputs, V
O
Package Thermal Impedance, q
JA
Storage Temperature, T
STG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCO
I
EE
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
122
Maximum
3.465
3.465
150
Units
V
V
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Current
Input Low Current
Input High Current
Input Low Current
CLK_EN,
CLK_SEL
CLK_EN,
CLK_SEL
CLK_SEL
CLK_EN
CLK_SEL
CLK_EN
Test Conditions
Minimum
2
-0.3
V
IN
= V
CC
= 3.465V
V
IN
= V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
-5
-150
Typical
Maximum
V
CC
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
CLK
nCLK
CLK
nCLK
Test Conditions
V
IN
= V
CC
= 3.465V
V
IN
= V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
-5
-150
1.3
V
CC
- 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
V
EE
+ 0.5
V
CMR
NOTE 1, 2
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK and nCLK is V
CC
+ 0.3V.
8532BY-01
www.icst.com/products/hiperclocks.htlm
4
REV. A JUNE 26, 2002
Integrated
Circuit
Systems, Inc.
ICS8532BY-01
L
OW
S
KEW
, 1-
TO
-17
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
Test Conditions
PCLK
nPCLK
PCLK
nPCLK
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
0.3
V
EE
+ 1.5
V
CCO
- 1.4
V
CCO
- 2.0
1
V
CC
V
CCO
- 1.0
V
CCO
- 1.7
0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
V
V
V
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
V
CMR
V
OH
V
OL
Parameter
Input High Current
Input Low Current
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
Output High Voltage; NOTE 3
Output Low Voltage; NOTE 3
Peak-to-Peak Voltage Swing
0.6
V
SWING
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for PCLK, nPCLK is V
CC
+ 0.3V.
NOTE 3: Outputs terminated with 50
Ω
to V
CCO
- 2V.
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise Time
Output Fall Time
Output Duty Cycle
20% to 80% @ 50MHz
20% to 80% @ 50MHz
0
≤
IJ 266MHz
300
300
48
50
IJ 500MHz
1.3
Test Conditions
Minimum
Typical
Maximum
500
2.5
50
250
700
700
52
53
Units
MHz
ns
ps
ps
ps
ps
%
%
t
sk(o)
t
sk(pp)
t
R
t
F
odc
266
≤
IJ 500MHz
47
50
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8532BY-01
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5
REV. A JUNE 26, 2002
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