ZL10312
Satellite Demodulator
Data Sheet
Features
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Conforms to EBU specification for DVB-S and
DirecTV specification for DSS
On-chip digital filtering supports 1 - 45 MSps
symbol rates
On-chip 60 or 90 MHz dual-ADC
High speed scanning mode for blind symbol
rate/code rate acquisition
Automatic spectral inversion resolution
High level software interface for minimum
development time
Up to ±22 MHz LNB frequency tracking
DiSEqC™ v2.2: receive/transmit for full control of
LNB, dish and other components
Compact 64 pin LQFP package (7 x 7 mm)
Sleep pin gives ~1,000 fold reduction in power to
help products meet ENERGY STAR
®
requirements
ZL10312QCG
ZL10312QCF
ZL10312QCG1
ZL10312UBH
November 2004
Ordering Information
64 Pin LQFP
64 Pin LQFP
64 Pin LQFP*
Die supplied in
Trays, Bake & Drypack
Tape & Reel
Trays, Bake & Drypack
wafer form**
*Pb Free Matte Tin
**
Please contact Sales for further details
0°C to +70°C
Description
The ZL10312 is a QPSK/BPSK 1 - 45 MSps
demodulator and channel decoder for digital satellite
television transmissions to the European Broadcast
Union ETS 300 421 specification. It receives analogue
I and Q signals from the tuner, digitises and digitally
demodulates this signal, and implements the complete
DVB/DSS FEC (Forward Error Correction), and de-
scrambling function. The output is in the form of
MPEG2 or DSS transport stream data packets. The
ZL10312 also provides automatic gain control to the RF
front-end device.
The ZL10312 has a serial 2-wire bus interface to the
control microprocessor. Minimal software is required to
control the ZL10312 because of the built in automatic
search and decode control functions.
Applications
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DVB 1 - 45 MSps compliant satellite receiver
DSS 20 MSps compliant satellite receivers
SMATV trans-modulators. (Single Master
Antenna TV)
Satellite PC applications
I I/P
Dual ADC
Q I/P
De-rotator
Decimation
Filtering
Timing recovery
Matched filter
Phase recovery
DVB
DSS
FEC
MPEG/
DSS
Packets
Analog
AGC
Control
Clock Generation
Acquisition
Control
2-Wire Bus
Interface
Bus I/O
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.
ZL10312
Data Sheet
Figure 2 - ZL10312 Pin Allocation
Pin Table
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
Reset
DiSEqC[2]
DiSEqC[1]
DiSEqC[0]
Vdd
Gnd
CVdd
Gnd
Sleep
CLK1
DATA1
CVdd
Gnd
DATA2
CLK2
OscMode
No.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Name
CVdd
Gnd
XTI
XTO
Gnd
CVdd
Gnd
Iin
Iin
Gnd
Vdd
Gnd
Qin
Qin
Gnd
CVdd
No.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Name
Gnd
CVdd
Addr[1]
Addr[2]
Addr[3]
Addr[4]
Vdd
Gnd
AGC
Test
IRQ
CVdd
Gnd
MOSTRT
MOVAL
MDO[0]
No.
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Name
MDO[1]
CVdd
Gnd
MDO[2]
MDO[3]
Gnd
Vdd
MDO[4]
MDO[5]
Gnd
CVdd
MDO[6]
MDO[7]
MOCLK
BKERR
Status
Note: All supply pins
must
be connected as they are not all commoned internally.
2
Zarlink Semiconductor Inc.
ZL10312
Table of Contents
Data Sheet
1.0 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Analogue-to-Digital Converter and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 QPSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Forward Error Correction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Recommended Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Primary 2-Wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Crystal Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6 ZL10312 Pinout Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.7 Alphabetical Listing of Pin-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.0 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Zarlink Semiconductor Inc.
ZL10312
Overview
Data Sheet
The ZL10312 is a QPSK/BPSK 1 - 45 MSps demodulator and channel decoder for digital satellite television
transmissions compliant to both DVB-S and DSS standards and other systems.
A Command Driven Control (CDC) system is provided making the ZL10312 very simple to program. After the tuner
has been programmed to the required frequency to acquire a DVB transmission, the ZL10312 requires a minimum
of five registers to be written.
The ZL10312 provides a monitor of Bit Error Rate after the QPSK module and also after the Viterbi module. For
receiver installation, a high speed scan or 'blind search' mode is available. This allows all signals from a given
satellite to be evaluated for frequency, symbol rate and convolutional coding scheme. The phase of the IQ signals
can be automatically determined.
Full DiSEqC v2.x is provided for both writing and reading DiSEqC messages. Storage in registers for up to eight
data bytes sent and eight data bytes received is provided.
Additional Features
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2-wire bus microprocessor interface with
separate interface to tuner
All digital clock and carrier recovery
On-chip PLL clock generation using low cost 10
to 16 MHz crystal
Low power operation, with stand-by and sleep
modes
3.3 V operation with 1.8 V for core logic
7 x 7mm 64 pin LQFP package
Low external component count
Commercial temperature range 0 to 70°C
De-Interleaver
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Compliant with DVB and DSS standards
Reed Solomon
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(204, 188) for DVB and (146,130) for DSS
Reed Solomon bit-error-rate monitor to indicate
Viterbi performance
De-Scrambler
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EBU specification de-scrambler for DVB mode
Outputs
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MPEG transport parallel & serial output
Integrated MPEG2 TEI bit processing for DVB
only
Demodulator
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BPSK or QPSK programmable
Optional fast acquisition mode for low symbol
rates
Application Support
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Design Manual
Channel decoder system evaluation board
Windows based evaluation software
ANSI-C generic software
Viterbi
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Programmable decoder rates 1/2, 2/3, 3/4, 5/6,
6/7, 7/8
Automatic spectral inversion resolution
Constraint length k=7
Trace back depth 128
Extensive SNR and BER monitors
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Zarlink Semiconductor Inc.
ZL10312
Data Sheet
Figure 3 - Typical Application Schematic
5
Zarlink Semiconductor Inc.
Microcontroller MCU
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