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PRELIMINARY DATASHEET
DS3100
Stratum 3/3E Timing Card IC
www.maxim-ic.com
GENERAL DESCRIPTION
When paired with an external TCXO or OCXO, the
DS3100 is a complete central timing and
synchronization solution for SONET/SDH network
elements. With two multi-protocol BITS/SSU
receivers and fourteen input clocks, the device
directly accepts both external timing and line timing
from a large number of line cards. All input clocks are
continuously monitored for frequency accuracy and
activity. Any two of the input clocks can be selected
as the references for the two core DPLLs. The T0
DPLL complies with the stratum 3 and 3E
requirements of GR1244, GR-253, and the
requirements of G.812 Type III and G.813. From the
output of the core DPLLs a wide variety of output
clock frequencies and frame pulses can be produced
simultaneously on the eleven output clock pins. Two
DS3100 devices can be configured in a master/slave
arrangement for timing card equipment protection.
The DS3100 registers and I/O pins are backward
compatible with Semtech’s ACS8520 and ACS8530
timing card ICs.
FEATURES
Synchronization subsystem for stratum 3E, 3, 4E
and 4, SMC and SEC
- Meets requirements of GR-1244 stratum 3/3E,
GR-253, G.812 Types I and III, and G.813
- Stratum 3E holdover accuracy with suitable
external oscillator
- Programmable bandwidth, 0.5 mHz to 70 Hz
- Hitless reference switching on loss of input
- Phase build-out and transient absorption
- Locks to and generates 125 MHz for timing
over Gigabit Ethernet per ITU-T G.pactiming
Fourteen Input Clocks
- Ten CMOS/TTL inputs accept 2kHz, 4kHz and
any multiple of 8 kHz up to 125 MHz
- Two LVDS/LVPECL/CMOS/TTL inputs accept
Nx8 kHz up to 125 MHz plus 155.52 MHz
- Two 64 kHz Composite Clock receivers
- Continuous input clock quality monitoring
- Separate 2/4/8 kHz frame sync input
Eleven Output Clocks
- Five CMOS/TTL outputs drive any internally
produced clock up to 77.76 MHz
- Two LVDS outputs each drive any internally
produced clock up to 311.04 MHz
- One 64 kHz Composite Clock transmitter
- One 1.544 MHz / 2.048 MHz output clock
- Two sync pulses: 8 kHz and 2 kHz
- Output clock rates include 2 kHz, 8 kHz, NxDS1,
NxDS2, DS3, NxE1, E3, 6.48 MHz, 19.44 MHz,
38.88 MHz, 51.84 MHz, 62.5 MHz, 77.76 MHz,
125 MHz, 155.52 MHz, 311.04 MHz
Two multi-protocol BITS/SSU transceivers
- Receive and transmit DS1, E1, 2048 kHz, and
6312 kHz timing signals
- Insert and extract SSM messages (DS1, E1)
- Automatically invalidate clocks on LOS, OOF,
AIS and other defects
Internal compensation for master clock oscillator
frequency accuracy
Processor interface: 8-bit parallel or SPI serial
1.8V operation with 3.3V I/O (5V tolerant)
Industrial operating temperature range
APPLICATIONS
SONET/SDH ADMs, MSPPs, and MSSPs
Digital Cross-Connects
DSLAMs
Service Provider Routers
FUNCTIONAL DIAGRAM
timing from
line cards
(various rates)
timing from
BITS/SSU
(DS1, E1, CC, etc.)
local TCXO
or OCXO
14
2
DS3100
SONET/SDH
Synchronization
IC
2
timing to
BITS/SSU
(DS1, E1, CC, etc.)
timing to
line cards
(various rates)
11
control status
ORDERING INFORMATION
PART
DS3100GN#
DS3100GN+
TEMP
-40 to 85°C
-40 to 85°C
PACKAGE
17x17 mm CSBGA,
tin/lead
17x17 mm CSBGA,
lead free
REV: 052406
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DS3100 PRELIMINARY DATASHEET
TABLE OF CONTENTS
1
2
3
4
5
6
7
STANDARDS COMPLIANCE ............................................................................................................................... 7
BLOCK DIAGRAM ................................................................................................................................................ 8
APPLICATION EXAMPLE..................................................................................................................................... 9
DETAILED DESCRIPTION ................................................................................................................................... 9
DETAILED FEATURES....................................................................................................................................... 10
PIN DESCRIPTIONS .......................................................................................................................................... 13
FUNCTIONAL DESCRIPTION............................................................................................................................ 19
7.1
7.2
7.3
7.4
Overview.................................................................................................................................................... 19
Device Identification and Protection .......................................................................................................... 20
Local Oscillator and Master Clock Configuration ...................................................................................... 20
Input Clock Configuration .......................................................................................................................... 21
7.4.1
7.4.2
7.5
Signal Format Configuration......................................................................................................... 21
Frequency Configuration .............................................................................................................. 22
Input Clock Quality Monitoring .................................................................................................................. 23
7.5.1
7.5.2
7.5.3
7.5.4
Frequency Monitoring................................................................................................................... 23
Activity Monitoring ........................................................................................................................ 23
Selected Reference Activity Monitoring........................................................................................ 24
Composite Clock Inputs................................................................................................................ 24
7.6
Input Clock Priority, Selection and Switching ............................................................................................ 25
7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
7.6.6
Priority Configuration .................................................................................................................... 25
Automatic Selection Algorithm ..................................................................................................... 25
Forced Selection........................................................................................................................... 26
Ultra-Fast Reference Switching.................................................................................................... 26
External Reference Switching Mode ............................................................................................ 26
Output Clock Phase Continuity During Reference Switching....................................................... 26
7.7
DPLL Architecture and Configuration........................................................................................................ 27
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.7.6
7.7.7
7.7.8
7.7.9
T0 DPLL State Machine ............................................................................................................... 27
T4 DPLL State Machine ............................................................................................................... 30
Bandwidth..................................................................................................................................... 30
Damping Factor ............................................................................................................................ 31
Phase Detectors ........................................................................................................................... 31
Loss of Phase Lock Detection...................................................................................................... 32
Phase Monitor and Phase Build-Out ............................................................................................ 32
Input to Output Phase Adjustment ............................................................................................... 34
Phase Recalibration ..................................................................................................................... 34
7.7.10 Frequency and Phase Measurement ........................................................................................... 34
7.7.11 Input Wander and Jitter Tolerance ............................................................................................... 35
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7.7.12 Jitter and Wander Transfer........................................................................................................... 35
7.7.13 Output Jitter and Wander ............................................................................................................. 35
7.8
Output Clock Configuration ....................................................................................................................... 36
7.8.1
7.8.2
7.9
Signal Format Configuration......................................................................................................... 36
Frequency Configuration .............................................................................................................. 36
Equipment Redundancy Configuration...................................................................................................... 44
7.9.1
7.9.2
7.9.3
Master-Slave Pin Feature............................................................................................................. 44
Master-Slave Output Clock Phase Alignment .............................................................................. 45
Master-Slave Frame and Multi-Frame Alignment with the SYNC2K Pin ..................................... 45
7.10 Multi-Protocol BITS Transceivers.............................................................................................................. 47
7.10.1 Master Clock Connections ........................................................................................................... 47
7.10.2 Receiver Clock Connections ........................................................................................................ 48
7.10.3 Transmitter Clock Connections .................................................................................................... 49
7.10.4 Line Interface Unit ........................................................................................................................ 51
7.10.5 DS1 Synchronization Interface..................................................................................................... 57
7.10.6 E1 Synchronization Interface ....................................................................................................... 59
7.10.7 G.703 2048 kHz Synchronization Interface.................................................................................. 61
7.10.8 G.703 Appendix II 6312 kHz Japanese Synchronization Interface.............................................. 62
7.11 Composite Clock Receivers and Transmitter ............................................................................................ 63
7.11.1 IC1 and IC2 Receivers ................................................................................................................. 63
7.11.2 OC8 Transmitter ........................................................................................................................... 64
7.12 Microprocessor Interfaces ......................................................................................................................... 66
7.12.1 Parallel Interface Modes............................................................................................................... 66
7.12.2 SPI Interface Mode....................................................................................................................... 66
7.13 Reset Logic................................................................................................................................................ 68
7.14 Power Supply Considerations ................................................................................................................... 68
7.15 Initialization................................................................................................................................................ 69
8
REGISTER DESCRIPTIONS.............................................................................................................................. 70
8.1
8.2
8.3
8.4
8.5
9
Status Bits ................................................................................................................................................. 70
Configuration Fields................................................................................................................................... 70
Multi-Register Fields.................................................................................................................................. 70
Core Register Definitions........................................................................................................................... 71
BITS Transceiver Register Definitions .................................................................................................... 136
JTAG TEST ACCESS PORT AND BOUNDARY SCAN................................................................................... 187
9.1
9.2
9.3
9.4
JTAG Description .................................................................................................................................... 187
JTAG TAP Controller State Machine Description ................................................................................... 187
JTAG Instruction Register and Instructions............................................................................................. 189
JTAG Test Registers ............................................................................................................................... 190
10 ELECTRICAL CHARACTERISTICS ................................................................................................................. 191
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10.1 DC Characteristics................................................................................................................................... 191
10.2 Input Clock Timing................................................................................................................................... 195
10.3 Output Clock Timing ................................................................................................................................ 195
10.4 BITS Transceiver Timing ......................................................................................................................... 196
10.5 Parallel Interface Timing.......................................................................................................................... 198
10.6 SPI Interface Timing ................................................................................................................................ 201
10.7 JTAG Interface Timing............................................................................................................................. 202
11 PIN ASSIGNMENTS ......................................................................................................................................... 203
12 MECHANICAL INFORMATION ........................................................................................................................ 209
13 THERMAL INFORMATION ............................................................................................................................... 210
14 GLOSSARY....................................................................................................................................................... 210
15 ACRONYMS AND ABBREVIATIONS............................................................................................................... 211
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LIST OF FIGURES
Figure 2-1 DS3100 Functional Block Diagram ............................................................................................................ 8
Figure 3-1. Typical Application Example ..................................................................................................................... 9
Figure 7-1. T0 DPLL State Transition Diagram ......................................................................................................... 28
Figure 7-2. T4 DPLL State Transition Diagram ......................................................................................................... 30
Figure 7-3. DPLL Block Diagram ............................................................................................................................... 37
Figure 7-4. OC10 8 kHz Options ............................................................................................................................... 44
Figure 7-5. BITS Transceiver Block Diagram ............................................................................................................ 47
Figure 7-6. BITS Transceiver Master Clock PLL Block Diagram .............................................................................. 48
Figure 7-7. BITS Transmitter Clock Mux Block Diagram........................................................................................... 49
Figure 7-8. BITS Transceiver External Components................................................................................................. 51
Figure 7-9. Jitter Tolerance, DS1 Mode .................................................................................................................... 52
Figure 7-10. Jitter Tolerance, E1 and 2048 kHz Modes ............................................................................................ 53
Figure 7-11. Transmit Pulse Template, DS1 Mode ................................................................................................... 55
Figure 7-12. Transmit Pulse Template, E1 Mode...................................................................................................... 55
Figure 7-13. Transmit Pulse Template, 2048 kHz Mode ........................................................................................... 56
Figure 7-14. FAS/Si/RAI/Sa Source Logic................................................................................................................. 61
Figure 7-15. GR-378 Composite Clock Pulse Mask.................................................................................................. 65
Figure 7-16. SPI Clock Polarity and Phase Options.................................................................................................. 67
Figure 7-17. SPI Bus Transactions............................................................................................................................ 68
Figure 9-1. JTAG Block Diagram............................................................................................................................. 187
Figure 9-2. JTAG TAP Controller State Machine .................................................................................................... 189
Figure 10-1. Recommended Termination for LVDS Pins ........................................................................................ 192
Figure 10-2. Recommended Termination for LVPECL Pins.................................................................................... 193
Figure 10-3. Recommended External Components for AMI Composite Clock Pins ............................................... 194
Figure 10-4. BITS Receiver Timing Diagram........................................................................................................... 196
Figure 10-5. BITS Transmitter Timing Diagram....................................................................................................... 197
Figure 10-6. Parallel Interface Timing Diagram (Nonmultiplexed) .......................................................................... 199
Figure 10-7. Parallel Interface Timing Diagram (Multiplexed) ................................................................................. 200
Figure 10-8. SPI Interface Timing Diagram ............................................................................................................. 201
Figure 10-9. JTAG Timing Diagram......................................................................................................................... 202
Figure 11-1. DS3100 Pin Assignments, Left Half .................................................................................................... 207
Figure 11-2. DS3100 Pin Assignments, Right Half.................................................................................................. 208
Figure 12-1. Mechanical Dimensions—256-lead 17x17mm CSBGA ...................................................................... 209
LIST OF TABLES
Table 1-A. Applicable Telecom Standards .................................................................................................................. 7
Table 6-A. Input Clock Pin Descriptions .................................................................................................................... 13
Table 6-B. Output Clock Pin Descriptions ................................................................................................................. 13
Table 6-C. BITS Receiver Pin Descriptions............................................................................................................... 14
Table 6-D. BITS Transmitter Pin Descriptions........................................................................................................... 15
Table 6-E. Global Pin Descriptions............................................................................................................................ 16
Table 6-F. Parallel Interface Pin Descriptions .......................................................................................................... 16
Table 6-G. SPI Bus Mode Pin Descriptions............................................................................................................... 17
Table 6-H. JTAG Interface Pin Descriptions.............................................................................................................. 17
Table 6-I. General Purpose IO Pin Descriptions ....................................................................................................... 18
Table 6-J. Power Supply Pin Descriptions ............................................................................................................... 18
Table 7-A. GR-1244 Stratum 3E/3 Stability Requirements ....................................................................................... 20
Table 7-B. Input Clock Capabilities............................................................................................................................ 21
Table 7-C. Locking Frequency Modes....................................................................................................................... 22
Table 7-D. Default Input Clock Priorities ................................................................................................................... 25
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