AT49LV001-70JL datasheet, PDF - EEWORLD Datasheet

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AT49LV001-70JL: DescriptionFlash, 128KX8, 70ns, PQCC32, PLASTIC, MS-016AE, LCC-32; Categorystorage storage; File Size441KB，25 Pages; ManufacturerAtmel (Microchip); Environmental Compliance

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AT49LV001-70JL Overview

Flash, 128KX8, 70ns, PQCC32, PLASTIC, MS-016AE, LCC-32

AT49LV001-70JL Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Atmel (Microchip)
Parts packaging code	QFJ
package instruction	QCCJ,
Contacts	32
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	70 ns
JESD-30 code	R-PQCC-J32
JESD-609 code	e3
length	13.97 mm
memory density	1048576 bit
Memory IC Type	FLASH
memory width	8
Humidity sensitivity level	2
Number of functions	1
Number of terminals	32
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX8
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	245
Programming voltage	3 V
Certification status	Not Qualified
Maximum seat height	3.556 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	MATTE TIN
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
type	NOR TYPE
width	11.43 mm

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Features

•

Single Supply for Read and Write: 2.7 to 3.6V (BV), 3.0 to 3.6V (LV)

Fast Read Access Time – 70 ns

Internal Program Control and Timer

Sector Architecture

– One 16-Kbyte Boot Block with Programming Lockout

– Two 8-Kbyte Parameter Blocks

– Two Main Memory Blocks (32K, 64K Bytes)

Fast Erase Cycle Time – 10 Seconds

Byte-by-byte Programming – 30 µs/Byte Typical

Hardware Data Protection

DATA Polling for End of Program Detection

Low Power Dissipation

– 25 mA Active Current

– 50 µA CMOS Standby Current

Typical 10,000 Write Cycles

•

Description

The AT49BV/LV001(N)(T) is a 3-volt-only in-system reprogrammable Flash memory.

Its 1 megabit of memory is organized as 131,072 words by 8 bits. Manufactured with

Atmel’s advanced nonvolatile CMOS technology, the device offers access times to

70 ns with power dissipation of just 90 mW over the commercial temperature range.

When the device is deselected, the CMOS standby current is less than 50 µA. For the

1-megabit

(128K x 8)

Single 2.7-volt

Battery-Voltage

™

Flash Memory

AT49BV001

AT49LV001

AT49BV001N

AT49LV001N

AT49BV001T

AT49LV001T

AT49BV001NT

AT49LV001NT

Not Recommended

for New Design

Contact

Atmel to discuss

the latest design in trends

and options

Pin Configurations

Pin Name

A0 - A16

RESET

I/O0 - I/O7

Function

Addresses

Chip Enable

Output Enable

Write Enable

RESET

Data Inputs/Outputs

Don’t Connect

No Connect

DIP Top View

*RESET

A16

A15

A12

I/O0

I/O1

I/O2

GND

VCC

A14

A13

A11

A10

I/O7

I/O6

I/O5

I/O4

I/O3

PLCC Top View

A12

A15

A16

RESET*

VCC

VSOP Top View (8 x 14mm) or

TSOP Top View (8 x 20mm) – Type 1

A11

A13

A14

VCC

*RESET

A16

A15

A12

A10

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

I/O1

I/O2

GND

I/O3

I/O4

I/O5

I/O6

I/O0

A14

A13

A11

A10

I/O7

1110C–FLASH–9/03

Note:

*This pin is a DC on the AT49BV001N(T) and AT49LV001N(T).

AT49BV/LV001(N)(T)

Device

Operation

READ:

The AT49BV/LV001(N)(T) is accessed like an EPROM. When CE and OE are low and

WE is high, the data stored at the memory location determined by the address pins is asserted

on the outputs. The outputs are put in the high impedance state whenever CE or OE is high.

This dual-line control gives designers flexibility in preventing bus contention.

COMMAND SEQUENCES:

When the device is first powered on it will be reset to the read or

standby mode depending upon the state of the control line inputs. In order to perform other

device functions, a series of command sequences are entered into the device. The command

sequences are shown in the Command Definitions table. The command sequences are written

by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high.

The address is latched on the falling edge of CE or WE, whichever occurs last. The data is

latched by the first rising edge of CE or WE. Standard microprocessor write timings are used.

The address locations used in the command sequences are not affected by entering the com-

mand sequences.

RESET:

A RESET input pin is provided to ease some system applications. When RESET is at

a logic high level, the device is in its standard operating mode. A low level on the RESET input

halts the present device operation and puts the outputs of the device in a high impedance

state. If the RESET pin makes a high-to-low transition during a program or erase operation,

the operation may not be successfully completed and the operation will have to be repeated

after a high level is applied to the RESET pin. When a high level is reasserted on the RESET

pin, the device returns to the read or standby mode, depending upon the state of the control

inputs. By applying a 12V ± 0.5V input signal to the RESET pin, the boot block array can be

reprogrammed even if the boot block lockout feature has been enabled (see Boot Block Pro-

gramming Lockout Override section). The RESET feature is not available on the

AT49BV/LV001N(T).

ERASURE:

Before a byte can be reprogrammed, the main memory block or parameter block

which contains the byte must be erased. The erased state of the memory bits is a logical “1”.

The entire device can be erased at one time by using a 6-byte software code. The software

chip erase code consists of 6-byte load commands to specific address locations with a specific

data pattern (please refer to the Chip Erase Cycle Waveforms).

After the software chip erase has been initiated, the device will internally time the erase opera-

tion so that no external clocks are required. The maximum time needed to erase the whole

chip is t

. If the boot block lockout feature has been enabled, the data in the boot sector will

not be erased.

CHIP ERASE:

If the boot block lockout has been enabled, the Chip Erase function will erase

Parameter Block 1, Parameter Block 2, Main Memory Block 1, and Main Memory Block 2 but

not the boot block. If the Boot Block Lockout has not been enabled, the Chip Erase function

will erase the entire chip. After the full chip erase the device will return back to read mode. Any

command during chip erase will be ignored.

1110C–FLASH–9/03

SECTOR ERASE:

As an alternative to a full chip erase, the device is organized into sectors

that can be individually erased. There are two 8-Kbyte parameter block sections and two main

memory blocks. The 8-Kbyte parameter block sections can be independently erased and

reprogrammed. The two main memory sections are designed to be used as alternative mem-

ory sectors. That is, whenever one of the blocks has been erased and reprogrammed, the

other block should be erased and reprogrammed before the first block is again erased. The

Sector Erase command is a six bus cycle operation. The sector address is latched on the fall-

ing WE edge of the sixth cycle while the 30H data input command is latched at the rising edge

of WE. The sector erase starts after the rising edge of WE of the sixth cycle. The erase opera-

tion is internally controlled; it will automatically time to completion.

BYTE PROGRAMMING:

Once the memory array is erased, the device is programmed (to a

logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be programmed back to

a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the

internal device command register and is a 4-bus cycle operation (please refer to the Com-

mand Definitions table). The device will automatically generate the required internal program

pulses.

The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs

last, and the data latched on the rising edge of WE or CE, whichever occurs first. Program-

ming is completed after the specified t

cycle time. The DATA polling feature may also be

used to indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT:

The device has one designated block that has

a programming lockout feature. This feature prevents programming of data in the designated

block once the feature has been enabled. The size of the block is 16K bytes. This block,

referred to as the boot block, can contain secure code that is used to bring up the system.

Enabling the lockout feature will allow the boot code to stay in the device while data in the rest

of the device is updated. This feature does not have to be activated; the boot block’s usage as

a write protected region is optional to the user. The address range of the boot block is 00000

to 03FFF for the AT49BV/LV001(N) while the address range of the boot block is 1C000 to

1FFFF for the AT49BV/LV001(N)T.

Once the feature is enabled, the data in the boot block can no longer be erased or pro-

grammed with input voltage level of 5.5V or less. Data in the main memory block can still be

changed through the regular programming method. To activate the lockout feature, a series of

six program commands to specific addresses with specific data must be performed. Please

refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION:

A software method is available to determine if pro-

gramming of the boot block section is locked out. When the device is in the software product

identification mode (see Software Product Identification Entry and Exit sections) a read from

address location 00002H will show if programming the boot block is locked out for the

AT49BV/LV001(N) and a read from address 1C002H will show if programming the boot block

is locked out for the AT49BV/LV001(N)T. If the data on I/O0 is low, the boot block can be pro-

grammed; if the data on I/O0 is high, the program lockout feature has been activated and the

block cannot be programmed. The software product identification code should be used to

return to standard operation.

AT49BV/LV001(N)(T)

1110C–FLASH–9/03

AT49BV/LV001(N)(T)

BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:

The user can override the boot

block programming lockout by taking the RESET pin to 12 volts during the entire chip erase,

sector erase or byte programming operation. When the RESET pin is brought back to TTL lev-

els the boot block programming lockout feature is again active. This feature is not available on

the AT49BV/LV001N(T).

PRODUCT IDENTIFICATION:

The product identification mode identifies the device and man-

ufacturer as Atmel. It may be accessed by hardware or software operation. The hardware

operation mode can be used by an external programmer to identify the correct programming

algorithm for the Atmel product.

For details, see Operating Modes (for hardware operation) or Software Product Identification.

The manufacturer and device code is the same for both modes.

DATA POLLING:

The AT49BV/LV001(N)(T) features DATA polling to indicate the end of a

program cycle. During a program cycle an attempted read of the last byte loaded will result in

the complement of the loaded data on I/O7. Once the program cycle has been completed, true

data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time

during the program cycle.

TOGGLE BIT:

In addition to DATA polling the AT49BV/LV001(N)(T) provides another method

for determining the end of a program or erase cycle. During a program or erase operation,

successive attempts to read data from the device will result in I/O6 toggling between one and

zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be

read. Examining the toggle bit may begin at any time during a program cycle.

HARDWARE DATA PROTECTION:

Hardware features protect against inadvertent programs

to the AT49BV/LV001(N)(T) in the following ways: (a) V

sense: if V

is below 1.8V (typical),

the program function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or

WE high inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE

or CE inputs will not initiate a program cycle.

1110C–FLASH–9/03

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