74HCT107D datasheet, PDF - EEWORLD Datasheet

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74HCT107D: DescriptionJ-K Flip-Flop, HCT Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO14; Categorylogic logic; File Size200KB，18 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com; Environmental Compliance

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74HCT107D Overview

J-K Flip-Flop, HCT Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO14

74HCT107D Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Nexperia
package instruction	SOP,
Reach Compliance Code	compliant
series	HCT
JESD-30 code	R-PDSO-G14
JESD-609 code	e4
length	8.65 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	J-K FLIP-FLOP
Humidity sensitivity level	1
Number of digits	2
Number of functions	2
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	54 ns
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
Trigger type	NEGATIVE EDGE
width	3.9 mm
minfmax	60 MHz

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74HC107; 74HCT107

Dual JK flip-flop with reset; negative-edge trigger

Rev. 5 — 30 November 2015

Product data sheet

1. General description

The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring

individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q

outputs. The reset is an asynchronous active LOW input and operates independently of

the clock input. The J and K inputs control the state changes of the flip-flops as described

in the mode select function table. The J and K inputs must be stable one set-up time prior

to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp

diodes that enable the use of current limiting resistors to interface inputs to voltages in

excess of V

2. Features and benefits



Complies with JEDEC standard no. 7A



Input levels:



The 74HC107: CMOS levels



The 74HCT107: TTL levels



ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-A exceeds 200 V



Multiple package options



Specified from

40 C

to +85

C

and from

40 C

to +125

C

3. Ordering information

Table 1.

Ordering information

Package

Temperature range

74HC107D

74HCT107D

74HC107DB

74HC107PW

40 C

to +125

C

40 C

to +125

C

SSOP14

TSSOP14

40 C

to +125

C

Name

SO14

Description

plastic small outline package; 14 leads; body width

3.9 mm

plastic shrink small outline package; 14 leads; body

width 5.3 mm

Version

SOT108-1

SOT337-1

Type number

plastic thin shrink small outline package; 14 leads; body SOT402-1

width 4.4 mm

74HCT107D Related Products

	74HCT107D	74HC107D	74HC107PW	74HC107DB
Description	J-K Flip-Flop, HCT Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO14	J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO14	J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO14	J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO14
Is it Rohs certified?	conform to	conform to	conform to	conform to
Maker	Nexperia	Nexperia	Nexperia	Nexperia
package instruction	SOP,	SOP,	TSSOP,	SSOP,
Reach Compliance Code	compliant	compliant	compliant	compliant
series	HCT	HC/UH	HC/UH	HC/UH
JESD-30 code	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14
JESD-609 code	e4	e4	e4	e4
length	8.65 mm	8.65 mm	5 mm	6.2 mm
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP
Humidity sensitivity level	1	1	1	1
Number of digits	2	2	2	2
Number of functions	2	2	2	2
Number of terminals	14	14	14	14
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
Output polarity	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP	TSSOP	SSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260	260	260	260
propagation delay (tpd)	54 ns	48 ns	48 ns	48 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.75 mm	1.75 mm	1.1 mm	2 mm
Maximum supply voltage (Vsup)	5.5 V	6 V	6 V	6 V
Minimum supply voltage (Vsup)	4.5 V	2 V	2 V	2 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	30	30	30
Trigger type	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE
width	3.9 mm	3.9 mm	4.4 mm	5.3 mm
minfmax	60 MHz	60 MHz	60 MHz	60 MHz

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