7476FCQR datasheet, PDF - EEWORLD Datasheet

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7476FCQR: DescriptionJ-K Flip-Flop, 2-Func, Master-slave Triggered, TTL, CDFP16,; Categorylogic logic; File Size229KB，6 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/

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7476FCQR Overview

J-K Flip-Flop, 2-Func, Master-slave Triggered, TTL, CDFP16,

7476FCQR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Fairchild
package instruction	DFP, FL16,.3
Reach Compliance Code	compliant
JESD-30 code	R-XDFP-F16
JESD-609 code	e0
Logic integrated circuit type	J-K FLIP-FLOP
Humidity sensitivity level	2A
Number of functions	2
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	CERAMIC
encapsulated code	DFP
Encapsulate equivalent code	FL16,.3
Package shape	RECTANGULAR
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	250
power supply	5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	TTL
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
Trigger type	MASTER-SLAVE
Base Number Matches	1

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Description	J-K Flip-Flop, 2-Func, Master-slave Triggered, TTL, CDFP16,	J-K Flip-Flop, 2-Func, Master-slave Triggered, TTL, PDIP16,	J-K Flip-Flop, 2-Func, Master-slave Triggered, TTL, PDIP16,	J-K Flip-Flop, 2-Func, Master-slave Triggered, TTL, CDIP16,	J-K Flip-Flop, 2-Func, Master-slave Triggered, TTL, CDIP16,	J-K Flip-Flop, 2-Func, Master-slave Triggered, TTL, CDFP16,	J-K Flip-Flop, 2-Func, Master-slave Triggered, TTL, PDIP16,	J-K Flip-Flop, 2-Func, Master-slave Triggered, TTL, CDIP16,
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
package instruction	DFP, FL16,.3	DIP, DIP16,.3	DIP, DIP16,.3	DIP, DIP16,.3	DIP, DIP16,.3	DFP, FL16,.3	DIP, DIP16,.3	DIP, DIP16,.3
Reach Compliance Code	compliant	compliant	unknown	compliant	compliant	compliant	compli	compli
JESD-30 code	R-XDFP-F16	R-PDIP-T16	R-PDIP-T16	R-XDIP-T16	R-XDIP-T16	R-XDFP-F16	R-PDIP-T16	R-XDIP-T16
Logic integrated circuit type	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP
Humidity sensitivity level	2A	2A	2A	2A	2A	2A	2A	2A
Number of functions	2	2	2	2	2	2	2	2
Number of terminals	16	16	16	16	16	16	16	16
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	125 °C
Package body material	CERAMIC	PLASTIC/EPOXY	PLASTIC/EPOXY	CERAMIC	CERAMIC	CERAMIC	PLASTIC/EPOXY	CERAMIC
encapsulated code	DFP	DIP	DIP	DIP	DIP	DFP	DIP	DIP
Encapsulate equivalent code	FL16,.3	DIP16,.3	DIP16,.3	DIP16,.3	DIP16,.3	FL16,.3	DIP16,.3	DIP16,.3
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK	IN-LINE	IN-LINE	IN-LINE	IN-LINE	FLATPACK	IN-LINE	IN-LINE
Peak Reflow Temperature (Celsius)	250	250	250	250	250	250	250	250
power supply	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	NO	NO	NO	NO	YES	NO	NO
technology	TTL	TTL	TTL	TTL	TTL	TTL	TTL	TTL
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	MILITARY
Terminal form	FLAT	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	FLAT	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	1.27 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	1.27 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	30	30	30	30	30	30	30
Trigger type	MASTER-SLAVE	MASTER-SLAVE	MASTER-SLAVE	MASTER-SLAVE	MASTER-SLAVE	MASTER-SLAVE	MASTER-SLAVE	MASTER-SLAVE
Maker	Fairchild	Fairchild	Fairchild	-	-	Fairchild	Fairchild	Fairchild
JESD-609 code	e0	e0	e0	e0	e0	e0	-	-
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-	-
Base Number Matches	1	1	1	1	1	1	-	-
Certification status	-	Not Qualified	-	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified

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