The Leader in High Temperature
Semiconductor Solutions
CHT-7474 DATASHEET
High-Temperature, Dual D-Flip-Flop
General Description
The CHT-7474 is a dual positive-edge-
triggered D type Flip-flop. Data on the D
input is transferred to the output on a rising
edge of the clock impulse.
Rn and Sn are asynchronous reset and set.
On a low state, they operate on the outputs
regardless of the other inputs.
This circuit is designed assuring latchup-
free operation for all supply and tempera-
ture conditions.
The CHT-7474 can operate with supply
voltages from 3.3 to 5V (±10%).
Revision: 03.3
1-Oct-12
(Last Modified Date)
Features
Qualified from -55 to +225°C (Tj)
3.3 to 5V (±10%) supply voltages
Latchup-free at any supply and tem-
perature condition
Validated at 225°C for 30000 hours
(CDIL14) and 20000 hours (CSOIC16)
(and still on-going)
Available in DIL14and CSOIC16 her-
metic standard package
Applications
Well logging,
Automotive, Aeronautics & Aerospace
Harsh Environments
Package and Pin Configuration
DIL14
Rn1
D1
C1
Sn1
Q1
Qn1
VSS
1
14
Pin
Symbol
RN1
D1
C1
SN1
Q1
QN1
GND
QN2
Q2
SN2
C2
D2
RN2
VDD
Description
Reset of D-flip-flop 1
Input of D-flip-flop 1
Clock pulse of D-flip-flop 1
Set of D-flip-flop 1
Output of D-flip-flop 1
Inverted output of D-flip-flop 1
Circuit core ground terminal.
Inverted output of D-flip-flop 2
Output of D-flip-flop 2
Set of D-flip-flop 2
Clock pulse of D-flip-flop 2
Input of D-flip-flop 2
Reset of D-flip-flop 2
Circuit core power supply terminal.
VDD
Rn2
D2
C2
Sn2
Q2
Qn2
1
2
2
13
3
4
3
12
5
6
4
11
7
8
5
10
9
10
6
9
11
12
7
8
13
14
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Contact
CHT-7474 DATASHEET
: Gonzalo Picún (+32-10-489214)Oct.
12
SOIC16
Rn1
D1
C1
Sn1
Q1
Qn1
VSS
N.C.
1
16
Pin
Symbol
RN1
D1
C1
SN1
Q1
QN1
VSS
NC
NC
QN2
Q2
SN2
C2
D2
RN2
VDD
Description
Reset of D-flip-flop 1
Input of D-flip-flop 1
Clock pulse of D-flip-flop 1
Set of D-flip-flop 1
Output of D-flip-flop 1
Inverted output of D-flip-flop 1
Circuit core ground terminal.
Not connected
Not connected
Inverted output of D-flip-flop 2
Output of D-flip-flop 2
Set of D-flip-flop 2
Clock pulse of D-flip-flop 2
Input of D-flip-flop 2
Reset of D-flip-flop 2
Circuit core power supply terminal.
VDD
Rn2
D2
C2
Sn2
Q2
Qn2
N.C.
1
2
2
15
3
4
3
14
5
6
4
13
7
8
5
12
9
10
6
11
11
12
7
10
13
14
8
9
15
16
Function Table
INPUT
Sn
L
H
L
Sn
H
H
Rn
H
L
L
Rn
H
H
C
X
X
X
C
D
X
X
X
D
L
H
Q
H
L
L
Q(n+1)
L
H
OUTPUT
Qn
L
H
1
X
Qn(n+1)
H
L
1
Having Sn=Rn=LOW at the same time should be avoided. The only known output is Q.
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CHT-7474 DATASHEET
: Gonzalo Picún (+32-10-489214)Oct.
12
Absolute Maximum Ratings
Supply Voltage V
DD
to GND
Voltage on any Pin to GND
ESD Rating (expected)
Human Body Model
-0.5 to 6.0V
-0.5 to V
DD
+0.5V
1kV
Operating Conditions
Supply Voltage V
DD
to GND
Junction temperature
3.3V to 5V (±10%)
-55°C to +225°C
DC Electrical Characteristics
Unless otherwise stated: VDD=5V, T
j
=25°C.
Bold underlined
figures indicate values valid
over the whole temperature range (-55°C < T
j
< +225°C).
Parameter
Supply voltage
V
DD
Condition
Min
2.97
Typ
Max
5.5V
Units
V
V
DD
= 3.3V, T
j
=-55°C
20
V
DD
= 5V, T
j
=-55°C
Quiescent current
I
DD
V
DD
= 3.3V, T
j
=225°C
20
nA
2650
V
DD
= 5V, T
j
=225°C
3030
V
DD
= 3.3V, I
OH
<4mA (source)
Minimum HIGH level output
voltage
V
OH
V
DD
= 5V, I
OH
<4mA (source)
2.7
3.04
V
4.6
4.82
V
DD
= 3.3V, I
OL
<4mA (sink)
Maximum LOW level output
voltage
V
OL
V
DD
= 5V, I
OL
<4mA (sink)
0.28
0.5
V
0.20
0.4
V
DD
= 3.3V
Minimum HIGH level input
voltage
V
IH
V
DD
= 5V
2.4
2.10
V
3.7
3.49
V
DD
= 3.3V
Maximum LOW level input
voltage
V
IL
V
DD
= 5V
1.72
1.5
V
2.16
2.0
VI=VCC or GND, V
DD
= 3.3V
Input leakage current
(source / sink)
± I
I
VI=VCC or GND, V
DD
= 5V
±1
±35
nA
±2
±37
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Contact
CHT-7474 DATASHEET
: Gonzalo Picún (+32-10-489214)Oct.
12
AC Electrical Characteristics
Unless otherwise stated: VDD=5V, T
j
=25°C.
Bold underlined
figures indicate values valid
over the whole temperature range (-55°C < T
j
< +225°C).
Parameter
Propagation
delay
from C to Q, Qn
t
PHL
Condition
Temperature
T
j
=-55°C
C
L
=50pF
T
j
=25°C
T
j
=225°C
T
j
=-55°C
C
L
=50pF
T
j
=25°C
T
j
=225°C
T
j
=-55°C
C
L
=50pF
T
j
=25°C
T
j
=225°C
T
j
=-55°C
C
L
=50pF
T
j
=25°C
T
j
=225°C
T
j
=-55°C
C
L
=50pF
T
j
=25°C
T
j
=225°C
T
j
=-55°C
C
L
=50pF
T
j
=25°C
T
j
=225°C
T
j
=-55°C
Clock pulse width
t
w
C
L
=50pF
T
j
=25°C
T
j
=225°C
T
j
=-55°C
Set or reset pulse
width
t
w
C
L
=50pF
T
j
=25°C
T
j
=225°C
T
j
=-55°C
Removal time set or
reset
t
rem
C
L
=50pF
T
j
=25°C
T
j
=225°C
T
j
=-55°C
Set-up time D to C
t
su
C
L
=50pF
T
j
=25°C
T
j
=225°C
T
j
=-55°C
Hold time C to D t
h
C
L
=50pF
T
j
=25°C
T
j
=225°C
T
j
=-55°C
Maximum clock
pulse frequency f
max
C
L
=50pF
T
j
=25°C
T
j
=225°C
4
4
6
4
4
6
4
4
6
2
2
2
2
2
2
31
27
21
Min
Typ
12
14
19
11
12
17
9
10
15
11
12
18
13
14
17
19
20
23
2
2
3
2
2
3
2
2
3
1
1
1
1
1
1
63
55
40
MHz
ns
ns
ns
ns
ns
Max
21
25
33
20
21
30
16
18
27
20
21
32
17
18
22
25
26
30
ns
ns
ns
ns
ns
ns
Units
Propagation
delay
from Rn to Q, Qn
t
PHL
Propagation delay
from C to Q, Qn
t
PLH
Propagation delay
from Sn to Q, Qn
t
PLH
Output transition time
High to Low
t
THL
Output transition time
High to Low
t
TLH
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