AM29LV400BB-70FE datasheet, PDF

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AM29LV400BB-70FE: Description512KX8 FLASH 3V PROM, 70ns, PDSO48, REVERSE, TSOP-48; Categorystorage storage; File Size780KB，44 Pages; ManufacturerAMD; Websitehttp://www.amd.com

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AM29LV400BB-70FE Overview

512KX8 FLASH 3V PROM, 70ns, PDSO48, REVERSE, TSOP-48

AM29LV400BB-70FE Parametric

Parameter Name	Attribute value
Maker	AMD
Parts packaging code	TSOP
package instruction	TSOP1-R,
Contacts	48
Reach Compliance Code	unknown
Maximum access time	70 ns
Other features	CONFG AS 256K X 16; EMBEDDED ALGORITHMS; 20 YEAR DATA RETENTION; BOTTOM BOOT BLOCK
JESD-30 code	R-PDSO-G48
length	18.4 mm
memory density	4194304 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of terminals	48
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	512KX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP1-R
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
Programming voltage	3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
width	12 mm
Base Number Matches	1

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Am29LV400B

4 Megabit (512 K x 8-Bit/256 K x 16-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

Single power supply operation

— Full voltage range: 2.7 to 3.6 volt read and write

operations for battery-powered applications

— Regulated voltage range: 3.0 to 3.6 volt read and

write operations for compatibility with high

performance 3.3 volt microprocessors

Manufactured on 0.32 µm process technology

— Compatible with 0.5 µm Am29LV400 device

High performance

— Full voltage range: access times as fast as 70 ns

— Regulated voltage range: access times as fast as

55 ns

Ultra low power consumption (typical values at

5 MHz)

— 200 nA Automatic Sleep mode current

— 200 nA standby mode current

— 7 mA read current

— 15 mA program/erase current

Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

seven 64 Kbyte sectors (byte mode)

— One 8 Kword, two 4 Kword, one 16 Kword, and

seven 32 Kword sectors (word mode)

— Supports full chip erase

— Sector Protection features:

A hardware method of locking a sector to prevent

any program or erase operations within that sector

Sectors can be locked in-system or via

programming equipment

Temporary Sector Unprotect feature allows code

changes in previously locked sectors

Unlock Bypass Program Command

— Reduces overall programming time when issuing

multiple program command sequences

Top or bottom boot block configurations

available

Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

Minimum 1,000,000 write cycle guarantee per sector

20-year data retention at 125°C

— Reliable operation for the life of the system

Package option

— 48-ball FBGA

— 48-pin TSOP

— 44-pin SO

Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

Data# Polling and toggle bits

— Provides a software method of detecting program

or erase operation completion

Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting

program or erase cycle completion

Erase Suspend/Erase Resume

— Suspends an erase operation to read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation

Hardware reset pin (RESET#)

— Hardware method to reset the device to reading

array data

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Publication#

21523

Rev:

Amendment/+1

Issue Date:

November 8, 2000

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5

Special Handling Instructions for Fine Pitch Ball Grid

Array (FBGA) ............................................................................ 7

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9

Table 1. Am29LV400B Device Bus Operations ................................9

Reading Toggle Bits DQ6/DQ2 ............................................... 21

DQ5: Exceeded Timing Limits ................................................ 22

DQ3: Sector Erase Timer ....................................................... 22

Figure 6. Toggle Bit Algorithm........................................................ 22

Table 6. Write Operation Status ..................................................... 23

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 24

Figure 7. Maximum Negative Overshoot Waveform ...................... 24

Figure 8. Maximum Positive Overshoot Waveform........................ 24

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 24

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 9. I

CC1

Current vs. Time (Showing Active and Automatic

Sleep Currents) .............................................................................. 26

Figure 10. Typical I

CC1

vs. Frequency ........................................... 26

Word/Byte Configuration .......................................................... 9

Requirements for Reading Array Data ..................................... 9

Writing Commands/Command Sequences ............................ 10

Program and Erase Operation Status .................................... 10

Standby Mode ........................................................................ 10

Automatic Sleep Mode ........................................................... 10

RESET#: Hardware Reset Pin ............................................... 10

Output Disable Mode .............................................................. 11

Table 2. Am29LV400BT Top Boot Sector Address Table ...............11

Table 3. Am29LV400BB Bottom Boot Sector Address Table .........11

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 11. Test Setup..................................................................... 27

Table 7. Test Specifications ........................................................... 27

Figure 12. Input Waveforms and Measurement Levels ................. 27

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28

Read Operations .................................................................... 28

Figure 13. Read Operations Timings ............................................. 28

Autoselect Mode ..................................................................... 12

Table 4. Am29LV400B Autoselect Codes (High Voltage Method) ..12

Hardware Reset (RESET#) .................................................... 29

Figure 14. RESET# Timings .......................................................... 29

Sector Protection/Unprotection ............................................... 12

Figure 1. In-System Sector Protect/Unprotect Algorithms .............. 13

Word/Byte Configuration (BYTE#) ........................................ 30

Figure 15. BYTE# Timings for Read Operations............................ 30

Figure 16. BYTE# Timings for Write Operations............................ 30

Temporary Sector Unprotect .................................................. 14

Figure 2. Temporary Sector Unprotect Operation........................... 14

Erase/Program Operations ..................................................... 31

Figure 17. Program Operation Timings..........................................

Figure 18. Chip/Sector Erase Operation Timings ..........................

Figure 19. Data# Polling Timings (During Embedded Algorithms).

Figure 20. Toggle Bit Timings (During Embedded Algorithms)......

Figure 21. DQ2 vs. DQ6.................................................................

Figure 22. Temporary Sector Unprotect Timing Diagram ..............

Figure 23. Sector Protect/Unprotect Timing Diagram ....................

Figure 24. Alternate CE# Controlled Write Operation Timings ......

Hardware Data Protection ...................................................... 14

Low V

Write Inhibit .............................................................. 14

Write Pulse “Glitch” Protection ............................................... 14

Logical Inhibit .......................................................................... 14

Power-Up Write Inhibit ............................................................ 14

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 15

Reading Array Data ................................................................ 15

Reset Command ..................................................................... 15

Autoselect Command Sequence ............................................ 15

Word/Byte Program Command Sequence ............................. 15

Unlock Bypass Command Sequence ..................................... 16

Figure 3. Program Operation .......................................................... 16

Chip Erase Command Sequence ........................................... 16

Sector Erase Command Sequence ........................................ 17

Erase Suspend/Erase Resume Commands ........................... 17

Figure 4. Erase Operation............................................................... 18

Command Definitions ............................................................. 19

Table 5. Am29LV400B Command Definitions .................................19

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 20

DQ7: Data# Polling ................................................................. 20

Figure 5. Data# Polling Algorithm ................................................... 20

RY/BY#: Ready/Busy# ........................................................... 21

DQ6: Toggle Bit I .................................................................... 21

DQ2: Toggle Bit II ................................................................... 21

Erase And Programming Performance . . . . . . . 39

Latchup Characteristics . . . . . . . . . . . . . . . . . . . 39

TSOP And SO Pin Capacitance . . . . . . . . . . . . . 39

Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 40

TS 048—48-Pin Standard TSOP ............................................ 40

TSR048—48-Pin Reverse TSOP ........................................... 41

FBA048—48-ball Fine-Pitch Ball Grid Array (FBGA)

6 x 8 mm package .................................................................. 42

SO 044—44-Pin Small Outline Package ............................... 43

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 44

Revision A (January 1998) ..................................................... 44

Revision B (July 1998) ............................................................ 44

Revision B+1 (August 1998) ................................................... 44

Revision C (January 1999) ..................................................... 44

Revision C+1 (July 2, 1999) ................................................... 44

Revision D (January 3, 1999) ................................................. 44

Revision D+1 (November 8, 2000) ......................................... 44

Am29LV400B

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