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4,032 Logic Cells
583,008 Max System Gates
Up to 506 I/O Pins
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Nine Global Clock Networks:
One Dedicated
Eight Programmable
20 Quad-Net Networks—five per Quadrant
16 I/O Control—two per I/O Bank
Four phase locked loops
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ECUs provide integrated Multiply, Add, and
Accumulate Functions.
Performance SRAM Blocks
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Memory - Dual Port RAM
Embedded Computational Units
PLL
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High performance Enhanced I/O (EIO)—
less than 3 ns Tco
Programmable Slew Rate Control
Programmable I/O Standards:
LVTTL, LVCMOS, PCI, GTL+, SSTL2,
and SSTL3
Eight Independent I/O Banks
Three Register Configurations: Input,
Output, and Output Enable
High Speed Logic Cells
583K Gates
PLL
Memory - Dual Port RAM
PLL
Figure 1: EclipsePlus Block Diagram
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The AC Specifications are provided from
7DEOH
to
7DEOH
. Logic Cell diagrams and
waveforms are provided from
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to
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.
Figure 2: EclipsePlus Logic Cell
7DEOH /RJLF &HOOV
6\PERO
/RJLF &HOOV
t
PD
t
SU
t
HL
t
CO
t
CWHI
t
CWLO
t
SET
Combinatorial Delay of the longest path: time taken by the combinatorial circuit to
output
Setup time: time the synchronous input of the flip-flop must be stable before the
active clock edge
Hold time: time the synchronous input of the flip-flop must be stable after the active
clock edge
Clock-to-out delay: the amount of time taken by the flip-flop to output after the
active clock edge.
Clock High Time: required minimum time the clock stays high
Clock Low Time: required minimum time that the clock stays low
Set Delay: time between when the flip-flop is ”set” (high)
and when the output is consequently “set” (high)
3DUDPHWHU
0LQ
-
0.22 ns
0 ns
-
0.46 ns
0.46 ns
-
9DOXH
0D[
0.257 ns
-
-
0.255 ns
-
-
0.18 ns
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t
RESET
t
SW
t
RW
Reset Delay: time between when the flip-flop is ”reset” (low) and when the output
is consequently “reset” (low)
Set Width: time that the SET signal remains high/low
Reset Width: time that the RESET signal remains high/low
3DUDPHWHU
0LQ
-
0.3 ns
0.3 ns
9DOXH
0D[
0.09 ns
-
-
SET
D
CLK
RESET
Q
Figure 3: Logic Cell Flip-Flop
CLK
tCWHI (min)
SET
tCWLO (min)
RESET
Q
tRESET
tRW
tSET
tSW
Figure 4: Logic Cell Flip-Flop Timings—First Waveform
CLK
D
tSU
tHL
Q
tCO
Figure 5: Logic Cell Flip-Flop Timings—Second Waveform
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Quad net
Figure 6: EclipsePlus Global Clock Structure
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*OREDO
Logic Cells (Internal)
Clock Pad
Clock signal generated internally
Clock signal generated externally
1.51 ns (max)
2.06 ns (max)
1.73 ns (max)
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7DEOH (FOLSVH3OXV *OREDO &ORFN 'HOD\
&ORFN 6HJPHQW
t
PGCKa
t
BGCK
3DUDPHWHU
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Global clock pin delay to quad net
Global clock tree delay
(quad net to flip-flop)
-
-
9DOXH
0D[
1.34 ns
0.56 ns
a.
When using a PLL, t
PGCK
and t
BGCK
are effectively zero due to delay adjustment by Phase Locked
Loop.
Programmable Clock
External Clock
Global Clock Buffer
Global Clock
Clock
Select
t
PGCK
t
BGCK
Figure 7: Global Clock Structure Schematic
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WA
WD
WE
WCLK
RE
RCLK
RA
RD
ASYNCRD
[9:0]
[17:0]
QuickRAM Module
Figure 8: RAM Module
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t
SWA
t
HWA
t
SWD
t
HWD
t
SWE
t
HWE
t
WCRD
WA setup time to WCLK: time the WRITE ADDRESS must be stable before the
active edge of the WRITE CLOCK
WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active
edge of the WRITE CLOCK
WD setup time to WCLK: time the WRITE DATA must be stable before the active
edge of the WRITE CLOCK
WD hold time to WCLK: time the WRITE DATA must be stable after the active edge
of the WRITE CLOCK
WE setup time to WCLK: time the WRITE ENABLE must be stable before the active
edge of the WRITE CLOCK
WE hold time to WCLK: time the WRITE ENABLE must be stable after the active
edge of the WRITE CLOCK
WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the
time when the data is available at RD
3DUDPHWHU
9DOXH
0LQ
0.675 ns
0ns
0.654 ns
0 ns
0.623 ns
0 ns
-
0D[
-
-
-
-
-
-
4.38 ns
WCLK
WA
tSWA
WD
tSWD
WE
tSWE
RD
old data
tWCRD
tHWE
new data
tHWD
tHWA
Figure 9: RAM Cell Synchronous Write Timing
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