PIC18F872X FAMILY
Flash Microcontroller Programming Specification
1.0
DEVICE OVERVIEW
2.1
Hardware Requirements
This document includes the programming specifications
for the following devices:
• PIC18F6527
• PIC18F6622
• PIC18F6627
• PIC18F6628
• PIC18F6722
• PIC18F6723
• PIC18F8527
• PIC18F8622
• PIC18F8627
• PIC18F8628
• PIC18F8722
• PIC18F8723
In High-Voltage ICSP mode, the PIC18F872X family
requires two programmable power supplies; one for
V
DD
and one for MCLR/V
PP
/RG5. Both supplies should
have a minimum resolution of 0.25V. Refer to
Section 6.0
“AC/DC
Characteristics
Timing
Requirements for Program/Verify Test Mode”
for
additional hardware parameters.
2.1.1
LOW-VOLTAGE ICSP™
PROGRAMMING
2.0
PROGRAMMING OVERVIEW
The PIC18F872X family of devices can be pro-
grammed using either the high-voltage In-Circuit Serial
Programming™ (ICSP™) method or the low-voltage
ICSP method. Both methods can be done with the
device in the users’ system. The low-voltage ICSP
method is slightly different than the high-voltage
method and these differences are noted where applica-
ble. This programming specification applies to the
PIC18F872X family of devices in all package types.
In Low-Voltage ICSP mode, the PIC18F872X family
can be programmed using a V
DD
source in the operat-
ing range. The MCLR/V
PP
/RG5 does not have to be
brought to a different voltage, but can instead be left at
the normal operating voltage. Refer to
Section 6.0
“AC/DC Characteristics Timing Requirements for
Program/Verify Test Mode”
for additional hardware
parameters.
2.2
Pin Diagrams
The pin diagrams for the PIC18F872X family are
shown in Figure 2-1 and Figure 2-2.
TABLE 2-1:
Pin Name
MCLR/V
PP
/RG5
V
DD
(1)
V
SS
(1)
AV
DD
AV
SS
RB5
RB6
RB7
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18F872X FAMILY
During Programming
Pin Name
V
PP
V
DD
V
SS
AV
DD
AV
SS
PGM
PGC
PGD
Pin Type
P
P
P
P
P
I
I
I/O
Programming Enable
Power Supply
Ground
Analog Power Supply
Analog Ground
Low-Voltage ICSP™ Input when LVP Configuration bit equals ‘1’
(2)
Serial Clock
Serial Data
Pin Description
Legend:
I = Input, O = Output, P = Power
Note 1:
All power supply (V
DD
) and ground (V
SS
) pins must be connected.
2:
See Table 5-1 for more information.
©
2009 Microchip Technology Inc.
DS39643C-page 1
PIC18F872X FAMILY
FIGURE 2-1:
PIC18F6527/6622/6627/6722/6628/6723 FAMILY PIN DIAGRAM
64-Pin TQFP
RD0
RD1
RD2
RD3
RD4
RD5
RD6
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RD7
RE2
RE3
RE4
RE5
RE6
RE7
V
DD
V
SS
RE1
RE0
RG0
RG1
RG2
RG3
MCLR/V
PP
/RG5
RG4
V
SS
V
DD
RF7
RF6
RF5
RF4
RF3
RF2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RB0
RB1
RB2
RB3
RB4
RB5/PGM
RB6/PGC
V
SS
RA6
RA7
V
DD
RB7/PGD
RC5
RC4
RC3
RC2
PIC18F6XXX
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RF1
RF0
AV
SS
RA3
RA2
RA5
RA4
RC1
RC0
RC6
AV
DD
RC7
RA1
RA0
V
SS
V
DD
DS39643C-page 2
©
2009 Microchip Technology Inc.
PIC18F872X FAMILY
FIGURE 2-2:
PIC18F8527/8622/8627/8722/8628/8723 FAMILY PIN DIAGRAM
80-Pin TQFP
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RH0
RH1
RD7
RE2
RE3
RE4
RE5
RE6
RE7
V
DD
RJ0
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RH2
RH3
RE1
RE0
RG0
RG1
RG2
RG3
MCLR/V
PP
/RG5
RG4
V
SS
V
DD
RF7
RF6
RF5
RF4
RF3
RF2
RH7
RH6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RJ2
RJ3
RB0
RB1
RB2
RB3
RB4
RB5/PGM
RB6/PGC
V
SS
RA6
RA7
V
DD
RB7/PGD
RC5
RC4
RC3
RC2
RJ7
RJ6
PIC18F8XXX
RF1
RF0
RJ4
AV
SS
RA3
RA2
RA5
RA4
RC1
RC0
RC6
RH5
RH4
AV
DD
©
2009 Microchip Technology Inc.
RC7
RA1
RA0
V
SS
V
DD
RJ5
RJ1
V
SS
DS39643C-page 3
PIC18F872X FAMILY
2.3
Memory Maps
TABLE 2-2:
Device
PIC18F6527
PIC18F8527
PIC18F6622
PIC18F8622
For PIC18F6622/8622 devices, the code memory
space extends from 000000h to 00FFFFh (64 Kbytes)
in four 16-Kbyte blocks. For PIC18F6527/8527
devices, the code memory space extends from
000000h to 00BFFFh (48 Kbytes) in three 16-Kbyte
blocks. Addresses, 0000h through 07FFh, however,
define a “Boot Block” region that is treated separately
from Block 0. All of these blocks define code protection
boundaries within the code memory space.
The size of the Boot Block in PIC18F6527/6622/8527/
8622 devices can be configured as 1, 2 or 4K words
(see Table 5-1). This is done through the BBSIZ<1:0>
bits in the Configuration register, CONFIG4L. It is
important to note that increasing the size of the Boot
Block decreases the size of Block 0.
IMPLEMENTATION OF CODE
MEMORY
Code Memory Size (Bytes)
000000h-00BFFFh (48K)
000000h-00FFFFh (64K)
FIGURE 2-3:
000000h
01FFFFh
MEMORY MAP AND THE CODE MEMORY SPACE
FOR PIC18F6527/6622/8527/8622 DEVICES
Code Memory
MEMORY SIZE/DEVICE
64 Kbytes
48 Kbytes
(PIC18F6622/8622) (PIC18F6527/8527)
Boot Block
Unimplemented
Read as ‘0’
Block 0
Block 1
Boot Block
Block 0
Block 1
007FFFh
008000h
Block 2
Block 2
00BFFFh
00C000h
Block 3
00FFFFh
010000h
013FFFh
Configuration
and ID
Space
014000h
Unimplemented
Read ‘0’s
Unimplemented
Read ‘0’s
017FFFh
018000h
01BFFFh
01C000h
01FFFFh
Address
Range
000000h
0007FFh* or 000FFFh* or 001FFFh*
000800h* or 001000h* or 002000h*
003FFFh
004000h
200000h
3FFFFFh
Note:
*
Sizes of memory areas are not to scale.
Boot Block size is determined by the BBSIZ<1:0> bits in CONFIG4L.
DS39643C-page 4
©
2009 Microchip Technology Inc.
PIC18F872X FAMILY
For PIC18F6722/8722/6723/8723 devices, the code
memory space extends from 000000h to 01FFFFh
(128 Kbytes) in eight 16-Kbyte blocks. For
PIC18F6627/8627/6628/8628 devices, the code mem-
ory space extends from 000000h to 017FFFh
(96 Kbytes) in six 16-Kbyte blocks. Addresses, 0000h
through 07FFh, however, define a “Boot Block” region
that is treated separately from Block 0. All of these
blocks define code protection boundaries within the
code memory space.
The size of the Boot Block in PIC18F6627/6722/8627/
8722/8723/8628/6723/6628 devices can be configured
as 1, 2 or 4K words (see Table 5-1). This is done through
the BBSIZ<1:0> bits in the Configuration register,
CONFIG4L. It is important to note that increasing the
size of the Boot Block decreases the size of Block 0.
TABLE 2-3:
Device
PIC18F6627
PIC18F8627
PIC18F6628
PIC18F8628
PIC18F6722
PIC18F8722
PIC18F6723
PIC18F8723
IMPLEMENTATION OF CODE
MEMORY
Code Memory Size (Bytes)
000000h-017FFFh (96K)
000000h-01FFFFh (128K)
FIGURE 2-4:
000000h
01FFFFh
MEMORY MAP AND THE CODE MEMORY SPACE
FOR PIC18F6627/6722/8627/8722/8723/8628/6723/6628 DEVICES
Code Memory
MEMORY SIZE/DEVICE
128 Kbytes
96 Kbytes
(PIC18F6722/8722) (PIC18F6627/8627)
Boot Block
Unimplemented
Read as ‘0’
Block 0
Block 1
Boot Block
Block 0
Block 1
007FFFh
008000h
Block 2
Block 2
00BFFFh
00C000h
Address
Range
000000h
0007FFh* or 000FFFh* or 001FFFh*
000800h* or 001000h* or 002000h*
003FFFh
004000h
200000h
Block 3
Block 3
00FFFFh
010000h
Block 4
Configuration
and ID
Space
Block 2
013FFFh
014000h
Block 5
Block 5
017FFFh
018000h
Block 6
Unimplemented
Read ‘0’s
Block 7
01FFFFh
01BFFFh
01C000h
3FFFFFh
Note:
*
Sizes of memory areas are not to scale.
Boot Block size is determined by the BBSIZ<1:0> bits in CONFIG4L.
©
2009 Microchip Technology Inc.
DS39643C-page 5
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