The PCS2I99448 is specifically designed to distribute
LVCMOS compatible clock signals up to a frequency of
350MHz. Each output provides a precise copy of the input
signal with a near zero skew. The outputs buffers support
driving of 50Ω terminated transmission lines on the incident
edge: each output is capable of driving either one parallel
terminated or two series terminated transmission lines.
Two selectable, independent clock inputs are available,
providing support of LVCMOS and differential LVPECL
clock distribution systems. The PCS2I99448 CLK_STOP
control is synchronous to the falling edge of the input clock.
It allows the start and stop of the output clock signal only in
a logic low state, thus eliminating potential output runt
pulses. Applying the OE control will force the outputs into
high–impedance mode.
All inputs have an internal pull–up or pull–down resistor
preventing unused and open inputs from floating. The
device supports a 2.5V or 3.3V power supply and an
ambient temperature range of –40°C to +85°C. The
PCS2I99448
is
pin
and
function
compatible
but
telecommunication and computing applications
•
Pin and Function compatible to MPC9448 and
MPC948
Functional Description
The PCS2I99448 is a 3.3V or 2.5V compatible, 1:12 clock
fanout buffer targeted for high performance clock tree
applications. With output frequencies up to 350 MHz and
output skews less than 150 pS, the device meets the needs
of most demanding clock applications.
performance–enhanced to the MPC948.
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
•
Tel: 408-879-9077
•
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
September 2006
rev 0.4
Block Diagram
PCS2I99448
V
CC
PCLK
PCLK
CCLK
Q0
Q1
Q2
Q3
Q4
0
1
CLK
STOP
V
CC
CLK_SEL
Q5
Q6
V
CC
CLK_STOP
SYNC
Q7
Q8
Q9
Q10
V
CC
OE
(All input resistors have a value of 25KΩ)
Q11
Pin Diagram
GND
V
CC
GND
V
CC
18
Q4
Q5
Q6
Q7
17
16
15
14
GND
Q8
V
CC
Q9
GND
Q10
V
CC
Q11
13
12
11
10
9
1
2
3
4
5
6
7
8
GND
24
Q3
V
CC
Q2
GND
Q1
V
CC
Q0
GND
25
26
27
28
29
30
31
32
23
22
21
20
19
PCS2I99448
CCLK
PCLK
CLK_SEL
PCLK
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
CLK_STOP
V
CC
OE
2 of 15
September 2006
rev 0.4
Table 1. FUNCTION TABLE
Control
CLK_SEL
OE
CLK_STOP
PCS2I99448
Default
1
1
1
0
PECL differential input selected
Outputs disabled (high-impedance state)
1
Outputs synchronously stopped in logic low
state
CCLK input selected
Outputs enabled
Outputs active
1
Note: 1. OE=0 will high-impedance tristate all outputs independent on CLK_STOP.
Table 2. PIN CONFIGURATION
Pin#
4,3
2
1
5
6
31,29,27,25,23,21,19,17,15,13,11,9
8,12,16,20,24,28,32
7,10,14,18,22,26,30
Pin Name
PCLK, PCLK
CCLK
CLK_SEL
CLK_STOP
OE
Q0 – Q11
GND
V
CC
I/O
Input
Input
Input
Input
Input
Output
Supply
Supply
Type
LVPECL
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
V
CC
Function
LVPECL Clock Inputs
Alternative clock signal input
Clock input select
Clock output enable/disable
Output enable/disable
(high–impedance tristate)
Clock output
Negative power supply (GND) for
I/O and core.
Positive power supply for I/O and
core. All V
CC
pins must be
connected to the positive power
supply for correct operation
Table 3. ABSOLUTE MAXIMUM RATINGS
1
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
Stor
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature Range
-65
Parameter
Min
-0.3
-0.3
-0.3
Max
3.9
V
CC
+ 0.3
V
CC
+ 0.3
±20
±50
125
Unit
V
V
V
mA
mA
°C
Note: 1. These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
3 of 15
September 2006
rev 0.4
Table 4. GENERAL SPECIFICATIONS
Symbol
V
TT
MM
HBM
LU
C
PD
C
IN
PCS2I99448
Characteristic
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Latch–up Immunity
Power Dissipation Capacitance
Input Capacitance
Min
200
2000
200
Typ
V
CC
÷2
Max
Unit
V
V
V
mA
Condition
10
4.0
pF
pF
Per Output
Inputs
Table 5. DC CHARACTERISTICS
(V
CC
= 3.3V ± 5%, T
A
= –40°C to +85°C)
Symbol
V
IH
V
IL
V
PP
V
CMR1
II
N
V
OH
V
OL
Z
OUT
I
CCQ4
Characteristic
Input HIGH Voltage
Input LOW Voltage
Peak–to–Peak Input Voltage
Common Mode Range
Input Current
2
Output HIGH Voltage
Output LOW Voltage
Output Impedance
Maximum Quiescent Supply Current
PCLK
PCLK
Min
2.0
-0.3
250
1.1
2.4
Typ
Max
V
CC
+ 0.3
0.8
V
CC -
0.6
300
0.55
0.30
Unit
V
V
mV
V
µA
V
V
V
Ώ
mA
Condition
LVCMOS
LVCMOS
LVPECL
LVPECL
V
IN
= V
CC
or GND
I
OH
= –24mA
3
I
OL
= 24mA
3
I
OL
= 12mA
All V
CC
Pins
17
2.0
Note: 1. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
3. The PCS2I99448 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to
a termination voltage of V
TT
. Alternatively, the device drives up to two 50Ω series terminated transmission lines (for V
CC
=3.3V) or one 50Ω series
terminated transmission line (for V
CC
=2.5V).
4. I
CCQ
is the DC current consumption of the device with all outputs open and the input in its default state or open.
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
4 of 15
September 2006
rev 0.4
Table 6. AC CHARACTERISTICS
(V
CC
= 3.3V ± 5%, T
A
= –40°C to +85°C)
1
Symbol
f
ref
f
MAX
V
PP
V
CMR2
t
P, REF
t
r
, t
f
t
PLH/HL
t
PLH/HL
t
PLZ, HZ
t
PZL, LZ
t
S
PCS2I99448
Characteristics
Min
0
0
PCLK
PCLK
400
1.3
1.4
1.0
PCLK to any Q
CCLK to any Q
1.6
1.3
3
Typ
Max
350
350
1000
V
CC
-0.8
Unit
MHz
MHz
mV
V
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Condition
Input Frequency
Maximum Output Frequency
Peak-to-peak input voltage
Common Mode Range
Reference Input Pulse Width
CCLK Input Rise/Fall Time
Propagation delay
Output Disable Time
Output Enable Time
Setup time
CCLK to CLK_STOP
PCLK to CLK_STOP
LVPECL
LVPECL
0.8 to 2.0V
3.6
3.3
11
11
0.0
0.0
1.0
1.5
150
t
H
t
sk(O)
t
sk(PP)
t
SK(P)
DC
Q
t
r
, t
f
Hold time
Output-to-output Skew
Device-to-device Skew
Output pulse skew
Output Duty Cycle
Output Rise/Fall Time
4
CCLK to CLK_STOP
PCLK to CLK_STOP
PCLK or CCLK to any Q
Using CCLK
Using PCLK
f
Q
<170 MHz
pS
nS
pS
pS
%
nS
DC
REF
= 50%
0.55 to 2.4V
2.0
300
400
45
0.1
50
55
1.0
Note: 1. AC characteristics apply for parallel output termination of 50Ω to V
TT
.
2. V
CMR
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
CMR
range and the input
swing lies within the V
PP
(AC) specification. Violation of V
CMR
or V
PP
impacts t
PLH/HL
and t
SK(PP)
.
3. Violation of the 1.0 nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse
width, output duty cycle and maximum frequency specifications.
4. Output pulse skew is the absolute difference of the propagation delay times: | t
pLH
- t
pHL
|.
Table 7. DC CHARACTERISTICS
(V
CC
= 2.5V ± 5%, T
A
= –40°C to +85°C)
Symbol
V
IH
V
IL
V
PP
V
CMR1
I
IN
V
OH
V
OL
Z
OUT
I
CCQ4
Characteristics
Input high voltage
Input low voltage
Peak-to-peak input voltage
Common Mode Range
Input current
2
Output High Voltage
Output Low Voltage
Output impedance
Maximum Quiescent Supply Current
PCLK
PCLK
Min
1.7
-0.3
250
1.0
Typ
Max
V
CC
+ 0.3
0.7
V
CC
-0.7
300
Unit
V
V
mV
V
µA
V
V
Ω
mA
Condition
LVCMOS
LVCMOS
LVPECL
LVPECL
V
IN
=GND or
V
IN
=VCC
I
OH
= -15 mA
3
I
OL
= 15 mA
3
All V
CC
Pins
1.8
0.6
19
2.0
Note: 1. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
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