P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCs
Rev. 07 — 26 November 2008
Product data sheet
1. General description
The P89LPC933/934/935/936 is a single-chip microcontroller, available in low cost
packages, based on a high performance processor architecture that executes instructions
in two to four clocks, six times the rate of standard 80C51 devices. Many system-level
functions have been incorporated into the P89LPC933/934/935/936 in order to reduce
component count, board space, and system cost.
2. Features
2.1 Principal features
I
4 kB/8 kB/16 kB byte-erasable flash code memory organized into 1 kB/2 kB sectors
and 64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile
data storage.
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256-byte RAM data memory. Both the P89LPC935 and P89LPC936 also include a
512-byte auxiliary on-chip RAM.
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512-byte customer data EEPROM on chip allows serialization of devices, storage of
setup parameters, etc. (P89LPC935/936).
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Dual 4-input multiplexed 8-bit A/D converters/DAC outputs (P89LPC935/936, single
A/D on P89LPC933/934).Two analog comparators with selectable inputs and
reference source.
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Two 16-bit counter/timers (each may be configured to toggle a port output upon timer
overflow or to become a PWM output) and a 23-bit system timer that can also be used
as an RTC.
I
Enhanced UART with fractional baud rate generator, break detect, framing error
detection, and automatic address detection; 400 kHz byte-wide I
2
C-bus
communication port and SPI communication port.
I
Capture/Compare Unit (CCU) provides PWM, input capture, and output compare
functions (P89LPC935/936).
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High-accuracy internal RC oscillator option allows operation without external oscillator
components.The RC oscillator option is selectable and fine tunable.
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2.4 V to 3.6 V V
DD
operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
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28-pin TSSOP, PLCC, and HVQFN packages with 23 I/O pins minimum and up to 26
I/O pins while using on-chip oscillator and reset options.
NXP Semiconductors
P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
2.2 Additional features
I
A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns
for all instructions except multiply and divide when executing at 18 MHz. This is six
times the performance of the standard 80C51 running at the same clock frequency. A
lower clock frequency for the same performance results in power savings and reduced
EMI.
I
Serial flash In-Circuit Programming (ICP) allows simple production coding with
commercial EPROM programmers. Flash security bits prevent reading of sensitive
application programs.
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Serial flash In-System Programming (ISP) allows coding while the device is mounted
in the end application.
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In-Application Programming (IAP) of the flash code memory. This allows changing the
code in a running application.
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Watchdog timer with separate on-chip oscillator, requiring no external components.
The watchdog prescaler is selectable from eight values.
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Low voltage reset (brownout detect) allows a graceful system shutdown when power
fails. May optionally be configured as an interrupt.
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Idle and two different power-down reduced power modes. Improved wake-up from
Power-down mode (a LOW interrupt input starts execution). Typical power-down
current is 1
µA
(total power-down with voltage comparators disabled).
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Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent spurious
and incomplete resets. A software reset function is also available.
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Configurable on-chip oscillator with frequency range options selected by user
programmed flash configuration bits. Oscillator options support frequencies from
20 kHz to the maximum operating frequency of 18 MHz.
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Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator
allowing it to perform an oscillator fail detect function.
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Programmable port output configuration options: quasi-bidirectional, open drain,
push-pull, input-only.
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Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of
the pins match or do not match a programmable pattern.
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LED drive capability (20 mA) on all port pins. A maximum limit is specified for the
entire chip.
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Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns
minimum ramp times.
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Only power and ground connections are required to operate the
P89LPC933/934/935/936 when internal reset option is selected.
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Four interrupt priority levels.
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Eight keypad interrupt inputs, plus two additional external interrupt inputs.
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Schmitt trigger port inputs.
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Second data pointer.
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Emulation support.
P89LPC933_934_935_936_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 26 November 2008
2 of 75
NXP Semiconductors
P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
3. Product comparison overview
Table 1
highlights the differences between the four devices. For a complete list of device
features please see
Section 2 “Features”.
Table 1.
Device
P89LPC933
P89LPC934
P89LPC935
P89LPC936
Product comparison overview
Flash memory Sector size
4 kB
8 kB
8 kB
16 kB
1 kB
1 kB
1 kB
2 kB
ADC1
X
X
X
X
ADC0
-
-
X
X
CCU
-
-
X
X
Data EEPROM
-
-
X
X
4. Ordering information
Table 2.
Ordering information
Package
Name
P89LPC935FA
P89LPC933HDH
P89LPC933FDH
P89LPC934FDH
P89LPC935FDH
P89LPC936FDH
P89LPC935FHN
HVQFN28
plastic thermal enhanced very thin
quad flat package; no leads;
28 terminals; body 6
×
6
×
0.85 mm
SOT788-1
PLCC28
TSSOP28
Description
plastic leaded chip carrier; 28 leads
plastic thin shrink small outline
package; 28 leads; body width 4.4 mm
Version
SOT261-2
SOT361-1
Type number
4.1 Ordering options
Table 3.
Ordering options
Flash memory
4 kB
4 kB
8 kB
Temperature range
−40 °C
to +125
°C
−40 °C
to +85
°C
Frequency
0 MHz to 18 MHz
Type number
P89LPC933HDH
P89LPC933FDH
P89LPC935FA
P89LPC934FDH
P89LPC935FDH
P89LPC935FHN
P89LPC936FDH
16 kB
P89LPC933_934_935_936_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 26 November 2008
3 of 75
NXP Semiconductors
P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
5. Block diagram
P89LPC933/934/935/936
ACCELERATED 2-CLOCK 80C51 CPU
4 kb/8 kB/16 kB
CODE FLASH
256-BYTE
DATA RAM
512-BYTE
AUXILIARY RAM
512-BYTE
DATA EEPROM
(P89LPC935/936)
P3[1:0]
PORT 3
CONFIGURABLE I/Os
PORT 2
CONFIGURABLE I/Os
PORT 1
CONFIGURABLE I/Os
PORT 0
CONFIGURABLE I/Os
UART
internal bus
I
2
C-BUS
TXD
RXD
SCL
SDA
SPICLK
MOSI
MISO
SS
SPI
REAL-TIME CLOCK/
SYSTEM TIMER
TIMER 0
TIMER 1
T0
T1
CMP2
CIN2B
CIN2A
CMP1
CIN1A
CIN1B
OCA
OCB
OCC
OCD
ICA
ICB
AD10
AD11
AD12
AD13
DAC1
AD00
AD01
AD02
AD03
DAC1
P2[7:0]
ANALOG
COMPARATORS
P1[7:0]
P0[7:0]
CCU (CAPTURE/
COMPARE UNIT)
(P89LPC935/936)
KEYPAD
INTERRUPT
WATCHDOG TIMER
AND OSCILLATOR
ADC1/DAC1
PROGRAMMABLE
OSCILLATOR DIVIDER
CPU
clock
ADC0/DAC0
(P89LPC935/936)
CRYSTAL
OR
RESONATOR
X1
X2
CONFIGURABLE
OSCILLATOR
ON-CHIP
RC
OSCILLATOR
POWER MONITOR
(POWER-ON RESET,
BROWNOUT RESET)
002aab070
Fig 1.
Block diagram
P89LPC933_934_935_936_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 26 November 2008
4 of 75
NXP Semiconductors
P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
6. Pinning information
6.1 Pinning
P2.0/DAC0
P2.1
P0.0/CMP2/KBI0
P1.7
P1.6
P1.5/RST
V
SS
P3.1/XTAL1
P3.0/XTAL2/CLKOUT
1
2
3
4
5
6
7
8
9
28 P2.7
27 P2.6
26 P0.1/CIN2B/KBI1/AD10
25 P0.2/CIN2A/KBI2/AD11
24 P0.3/CIN1B/KBI3/AD12
23 P0.4/CIN1A/KBI4/DAC1/AD13
P89LPC933HDH
P89LPC933FDH
P89LPC934FDH
22 P0.5/CMPREF/KBI5
21 V
DD
20 P0.6/CMP1/KBI6
19 P0.7/T1/KBI7
18 P1.0/TXD
17 P1.1/RXD
16 P2.5/SPICLK
15 P2.4/SS
P1.4/INT1 10
P1.3/INT0/SDA 11
P1.2/T0/SCL 12
P2.2/MOSI 13
P2.3/MISO 14
002aab071
Fig 2.
P89LPC933/934 TSSOP28 pin configuration
P2.0/ICB/DAC0/AD03
P2.1/OCD/AD02
P0.0/CMP2/KBI0/AD01
P1.7/OCC/AD00
P1.6/OCB
P1.5/RST
V
SS
P3.1/XTAL1
P3.0/XTAL2/CLKOUT
1
2
3
4
5
6
7
8
9
28 P2.7/ICA
27 P2.6/OCA
26 P0.1/CIN2B/KBI1/AD10
25 P0.2/CIN2A/KBI2/AD11
24 P0.3/CIN1B/KBI3/AD12
23 P0.4/CIN1A/KBI4/DAC1/AD13
22 P0.5/CMPREF/KBI5
21 V
DD
20 P0.6/CMP1/KBI6
19 P0.7/T1/KBI7
18 P1.0/TXD
17 P1.1/RXD
16 P2.5/SPICLK
15 P2.4/SS
002aab072
P89LPC935FDH
P89LPC936FDH
P1.4/INT1 10
P1.3/INT0/SDA 11
P1.2/T0/SCL 12
P2.2/MOSI 13
P2.3/MISO 14
Fig 3.
P89LPC935/936 TSSOP28 pin configuration
P89LPC933_934_935_936_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 26 November 2008
5 of 75
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