CY2309AZC-1T datasheet, PDF - EEWORLD Datasheet

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CY2309AZC-1T: DescriptionPLL Based Clock Driver, 2309 Series, 9 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSSOP-16; Categorylogic logic; File Size68KB，9 Pages; ManufacturerCypress Semiconductor

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CY2309AZC-1T Overview

PLL Based Clock Driver, 2309 Series, 9 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSSOP-16

CY2309AZC-1T Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP16,.25
Contacts	16
Reach Compliance Code	not_compliant
series	2309
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G16
JESD-609 code	e0
length	5 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	16
Actual output times	9
Maximum operating temperature	70 °C
Minimum operating temperature
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP16,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.2 ns
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4.4 mm
minfmax	200 MHz
Base Number Matches	1

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CY2309A

Nine-Output, 200-MHz Zero Delay Buffer

Features

• 50-MHz to 200-MHz operating range

• 650-ps max. Total Timing Budget™ (TTB™) window

• Nine low-skew outputs, grouped as 4 + 4 + 1

— Output-output Skew < 200 ps

•

— Device-device Skew < 500 ps

Input-output skew < 250 ps

Cycle-cycle jitter < 100 ps

Three-stateable outputs

< 50-µA shutdown current

Spread Aware™

Phase-locked loop (PLL) bypass mode (see

Table 1)

16-pin TSSOP

3.3V operation

Commercial/Industrial temperature

rejection. These parameters are critical for reference clock

distribution in systems using high-performance ASICs and

microprocessors. The CY2309A PLL feedback is internal and

is connected to CLKOUT.

The device features a guaranteed maximum TTB window

specifying all occurrences of output clocks with respect to the

input reference clock across variations in output frequency,

supply voltage, operating temperature, input edge rate, and

process.

The CY2309A has two banks of four outputs each, which can

be controlled by the select inputs as shown in

Table 1.

If all the

output clocks are not required, Bank B can be three-stated.

The select inputs also allow the input clock to be directly

applied to the outputs for chip and system testing purposes

(PLL bypass mode).

The CY2309A PLL enters a power-down state when there are

no rising edges on the REF input. In this mode, all outputs are

three-stated and the PLL is turned off, resulting in less than

µA

of current draw. The PLL shuts down in two additional

cases, as shown in

Table 1.

The CY2309A is available in standard (–1) or high-drive (–1H)

output versions. The high-drive features faster rise and fall

times.

Description

The CY2309A is a high-performance 200-MHz zero delay

buffer designed for high-speed clock distribution. The

integrated PLL is designed for low jitter and optimized for noise

Block Diagram

Pin Configuration

TSSOP

Top View

PLL

MUX

CLKOUT

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

REF

CLKB1

CLKB2

GND

CLKB3

CLKB4

CLKOUT

CLKA1

CLKA2

GND

CLKA3

CLKA4

Select Input

Decoding

CLKB2

CLKB3

CLKB4

Cypress Semiconductor Corporation

Document #: 38-07378 Rev. *B

•

3901 North First Street

•

San Jose

CA 95134

•

408-943-2600

Revised March 5, 2003

CY2309AZC-1T Related Products

	CY2309AZC-1T	CY2309AZC-1	CY2309AZC-1H	CY2309AZC-1HT	CY2309AZI-1	CY2309AZI-1T	CY2309AZI-1HT	CY2309AZI-1H
Description	PLL Based Clock Driver, 2309 Series, 9 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSSOP-16	PLL Based Clock Driver, 2309 Series, 9 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSSOP-16	PLL Based Clock Driver, 2309 Series, 9 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSSOP-16	PLL Based Clock Driver, 2309 Series, 9 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSSOP-16	PLL Based Clock Driver, 2309 Series, 9 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSSOP-16	PLL Based Clock Driver, 2309 Series, 9 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSSOP-16	PLL Based Clock Driver, 2309 Series, 9 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSSOP-16	PLL Based Clock Driver, 2309 Series, 9 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSSOP-16
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Parts packaging code	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP
package instruction	TSSOP, TSSOP16,.25	TSSOP, TSSOP16,.25	TSSOP, TSSOP16,.25	TSSOP, TSSOP16,.25	4.40 MM, TSSOP-16	4.40 MM, TSSOP-16	4.40 MM, TSSOP-16	4.40 MM, TSSOP-16
Contacts	16	16	16	16	16	16	16	16
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant
series	2309	2309	2309	2309	2309	2309	2309	2309
Input adjustment	STANDARD	STANDARD	STANDARD	STANDARD	STANDARD	STANDARD	STANDARD	STANDARD
JESD-30 code	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16
JESD-609 code	e0	e0	e0	e0	e0	e0	e0	e0
length	5 mm	5 mm	5 mm	5 mm	5 mm	5 mm	5 mm	5 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Number of functions	1	1	1	1	1	1	1	1
Number of terminals	16	16	16	16	16	16	16	16
Actual output times	9	9	9	9	9	9	9	9
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	85 °C	85 °C	85 °C	85 °C
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP
Encapsulate equivalent code	TSSOP16,.25	TSSOP16,.25	TSSOP16,.25	TSSOP16,.25	TSSOP16,.25	TSSOP16,.25	TSSOP16,.25	TSSOP16,.25
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.2 ns	0.2 ns	0.2 ns	0.2 ns	0.2 ns	0.2 ns	0.2 ns	0.2 ns
Maximum seat height	1.1 mm	1.1 mm	1.1 mm	1.1 mm	1.1 mm	1.1 mm	1.1 mm	1.1 mm
Maximum supply voltage (Vsup)	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	4.4 mm	4.4 mm	4.4 mm	4.4 mm	4.4 mm	4.4 mm	4.4 mm	4.4 mm
minfmax	200 MHz	200 MHz	200 MHz	200 MHz	133 MHz	133 MHz	133 MHz	133 MHz

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