a
FEATURES
Automatically Senses Sample Frequencies
No Programming Required
Attenuates Sample Clock Jitter
3.3 V–5 V Input and 3.3 V Core Supply Voltages
Accepts 16-/18-/20-/24-Bit Data
Up to 192 kHz Sample Rate
Input/Output Sample Ratios from 7.75:1 to 1:8
Bypass Mode
Multiple AD1896 TDM Daisy-Chain Mode
Multiple AD1896 Matched-Phase Mode
142 dB Signal-to-Noise and Dynamic Range
(A-Weighted, 20 Hz–20 kHz BW)
Up to –133 dB THD + N
Linear Phase FIR Filter
Hardware Controllable Soft Mute
Supports 256 f
S
, 512 f
S
, or 768 f
S
Master
Mode Clock
Flexible 3-Wire Serial Data Port with Left-Justified,
I
2
S, Right-Justified (16-,18-, 20-, 24-Bits), and
TDM Serial Port Modes
Master/Slave Input and Output Modes
28-Lead SSOP Plastic Package
APPLICATIONS
Home Theater Systems, Studio Digital Mixers,
Automotive Audio Systems, DVD, Set-Top Boxes,
Digital Audio Effects Processors, Studio-to-Transmitter
Links, Digital Audio Broadcast Equipment,
DigitalTape Varispeed Applications
192 kHz Stereo Asynchronous
Sample Rate Converter
AD1896
*
FUNCTIONAL BLOCK DIAGRAM
GRPDLYS
RESET
VDD_IO VDD_CORE
MUTE_I
SDATA_I
SCLK_I
LRCLK_I
SMODE_IN_0
SMODE_IN_1
SMODE_IN_2
BYPASS
MUTE_O
CLOCK DIVIDER
ROM
WLNGTH_O_0
WLNGTH_O_1
SERIAL
INPUT
DIGITAL
PLL
FIR
FILTER
SERIAL
OUTPUT
FIFO
FS
OUT
FS
IN
AD1896
SDATA_O
SCLK_O
LRCLK_O
TDM_IN
SMODE_O_0
SMODE_O_1
MCLK_I
MSMODE_0
MSMODE_2
MCLK_O
MSMODE_1
port supports TDM mode for daisy-chaining multiple AD1896s to
a digital signal processor. The serial output data is dithered down
to 20, 18, or 16 bits when 20-, 18-, or 16-bit output data is se-
lected. The AD1896 sample rate converts the data from the
serial input port to the sample rate of the serial output port. The
sample rate at the serial input port can be asynchronous with
respect to the output sample rate of the output serial port. The
master clock to the AD1896, MCLK, can be asynchronous to
both the serial input and output ports.
MCLK can be generated either off-chip or on-chip by the AD1896
master clock oscillator. Since MCLK can be asynchronous to the
input or output serial ports, a crystal can be used to generate
MCLK internally to reduce noise and EMI emissions on the
board. When MCLK is synchronous to either the output or input
serial port, the AD1896 can be configured in a master mode where
MCLK is divided down and used to generate the left/right
and bit clocks for the serial port that is synchronous to MCLK.
The AD1896 supports master modes of 256
¥
f
S
, 512
¥
f
S
,
and 768
¥
f
S
for both input and output serial ports.
Conceptually, the AD1896 interpolates the serial input data by
a rate of 2
20
and samples the interpolated data stream by the
output sample rate. In practice, a 64-tap FIR filter with 2
20
polyphases, a FIFO, a digital servo loop that measures the time
difference between the input and output samples within 5 ps,
and a digital circuit to track the sample rate ratio are used to
perform the interpolation and output sampling. Refer to the
Theory of Operation section. The digital servo loop and sample
rate ratio circuit automatically track the input and output
sample rates.
(Continued on Page 17)
PRODUCT OVERVIEW
The AD1896 is a 24-bit, high performance, single-chip, second-
generation asynchronous sample rate converter. Based on Analog
Devices experience with its first asynchronous sample rate
converter, the AD1890, the AD1896 offers improved performance
and additional features. This improved performance includes a
THD + N range of –117 dB to –133 dB depending on the sample
rate and input frequency, 142 dB (A-Weighted) dynamic range,
192 kHz sampling frequencies for both input and output sample
rates, improved jitter rejection, and 1:8 upsampling and 7.75:1
downsampling ratios. Additional features include more serial
formats, a bypass mode, better interfacing to digital signal pro-
cessors, and a matched-phase mode.
The AD1896 has a 3-wire interface for the serial input and
output ports that supports left-justified, I
2
S, and right-justified
(16-, 18-, 20-, 24-bit) modes. Additionally, the serial output
*Patents
pending.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD1896–SPECIFICATIONS
TEST CONDITIONS, UNLESS OTHERWISE NOTED.
Supply Voltages
VDD_CORE
VDD_IO
Ambient Temperature
Input Clock
Input Signal
Measurement Bandwidth
Word Width
Load Capacitance
Input Voltage High
Input Voltage Low
Specifications subject to change without notice.
3.3 V
5.0 V or 3.3 V
25°C
30.0 MHz
1.000 kHz, 0 dBFS
20 to f
S_OUT
/2 Hz
24 Bits
50 pF
2.4 V
0.8 V
DIGITAL PERFORMANCE (VDD_CORE = 3.3 V
5%, VDD_IO = 5.0 V
10%)
Parameter
Resolution
Sample Rate @ MCLK_I = 30 MHz
Sample Rate (@ Other Master Clocks)
1
Sample Rate Ratios
Upsampling
Downsampling (Short GRPDLYS)
Downsampling (Long GRPDLYS)
Dynamic Range
2
(20 Hz to f
S_OUT
/2, 1 kHz, –60 dBFS Input) A-Weighted
Worst-Case (192 kHz:48 kHz)
44.1 kHz:48 kHz
48 kHz:44.1 kHz
48 kHz:96 kHz
44.1 kHz:192 kHz
96 kHz:48 kHz
192 kHz:32 kHz
(20 Hz to f
S_OUT
/2, 1 kHz, –60 dBFS Input) No Filter
Worst-Case (192 kHz:48 kHz)
44.1 kHz:48 kHz
48 kHz:44.1 kHz
48 kHz:96 kHz
44.1 kHz:192 kHz
96 kHz:48 kHz
192 kHz:32 kHz
Total Harmonic Distortion + Noise
2
(20 Hz to f
S_OUT
/2, 1 kHz, 0 dBFS Input) No Filter
Worst-Case (32 kHz:48 kHz)
3
44.1 kHz:48 kHz
48 kHz:44.1 kHz
48 kHz:96 kHz
44.1 kHz:192 kHz
96 kHz:48 kHz
192 kHz:32 kHz
Interchannel Gain Mismatch
Interchannel Phase Deviation
Mute Attenuation (24 Bits Word Width) (A-Weighted)
Min
Typ
24
Max
Unit
Bits
kHz
kHz
6
215
MCLK_I/5000
≤
f
S
< MCLK_I/138
1:8
7.75:1
7.0:1
132
142
141
142
141.5
140
140
132
139
139
139
137
137
138
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
–117
–123
–124
–120
–123
–132
–133
0.0
0.0
–144
dB
dB
dB
dB
dB
dB
dB
dB
Degrees
dB
NOTES
1
Lower sampling rates than given by this formula are possible, but the jitter rejection will decrease.
2
Refer to the Typical Performance Characteristics section for DNR and THD + N numbers over wide range of input and output sample rates.
3
For any other sample rate ratio, the minimum THD + N will be better than –117 dB. Please refer to detailed performance plots.
Specifications subject to change without notice.
–2–
REV. A
AD1896
DIGITAL TIMING (–40 C < T
A
< +105 C, VDD_CORE = 3.3 V
5%, VDD_IO = 5.0 V
10%)
Parameter
1
t
MCLKI
f
MCLK
t
MPWH
t
MPWL
MCLK_I Period
MCLK_I Frequency
MCLK_I Pulsewidth High
MCLK_I Pulsewidth Low
Min
33.3
Typ
Max
30.0
2, 3
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
9
12
8
8
8
8
3
12
12
3
3
20
3
5
3
10
5
200
12
12
Input Serial Port Timing
t
LRIS
LRCLK_I Setup to SCLK_I
SCLK_I Pulsewidth High
t
SIH
t
SIL
SCLK_I Pulsewidth Low
SDATA_I Setup to SCLK_I Rising Edge
t
DIS
SDATA_I Hold from SCLK_I Rising Edge
t
DIH
Propagation Delay from MCLK_I Rising Edge to SCLK_I Rising Edge
(Serial Input Port MASTER)
Propagation Delay from MCLK_I Rising Edge to LRCLK_I Rising Edge
(Serial Input Port MASTER)
Output Serial Port Timing
t
TDMS
TDM_IN Setup to SCLK_O Falling Edge
TDM_IN Hold from SCLK_O Falling Edge
t
TDMH
SDATA_O Propagation Delay from SCLK_O, LRCLK_O
t
DOPD
t
DOH
SDATA_O Hold from SCLK_O
LRCLK_O Setup to SCLK_O (TDM Mode Only)
t
LROS
LRCLK_O Hold from SCLK_O (TDM Mode Only)
t
LROH
t
SOH
SCLK_O Pulsewidth High
SCLK_O Pulsewidth Low
t
SOL
RESET Pulsewidth Low
t
RSTL
Propagation Delay from MCLK_I Rising Edge to SCLK_O Rising Edge
(Serial Output Port MASTER)
Propagation Delay from MCLK_I Rising Edge to LRCLK_O Rising Edge
(Serial Output Port MASTER)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1
Refer to Timing Diagrams section.
2
The maximum possible sample rate is:
FS
MAX
=
f
MCLK
/138.
3
f
MCLK
of up to 34 MHz is possible under the following conditions: 0∞C < T
A
< 70∞C, 45/55 or better MCLK_I duty cycle.
Specifications subject to change without notice.
REV. A
–3–
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